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https://github.com/YosysHQ/yosys
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Progress in Verific bindings
This commit is contained in:
Clifford Wolf
parent
77e5968323
commit
0ac915a757
3 changed files with 348 additions and 228 deletions
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@ -29,12 +29,18 @@
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#ifdef YOSYS_ENABLE_VERIFIC
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#pragma clang diagnostic push
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#pragma clang diagnostic ignored "-Woverloaded-virtual"
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#include "veri_file.h"
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#include "vhdl_file.h"
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#include "VeriWrite.h"
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#include "VeriModule.h"
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#include "VhdlUnits.h"
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#include "DataBase.h"
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#include "Message.h"
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#pragma clang diagnostic pop
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#ifdef VERIFIC_NAMESPACE
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using namespace Verific ;
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#endif
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@ -123,13 +129,288 @@ static RTLIL::SigSpec operatorOutput(Instance *inst, std::map<Net*, RTLIL::SigBi
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return sig;
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}
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static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*> &nl_todo)
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static bool import_netlist_instance_gates(RTLIL::Module *module, std::map<Net*, RTLIL::SigBit> &net_map, Instance *inst)
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{
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if (design->modules.count(RTLIL::escape_id(nl->Owner()->Name())))
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log_cmd_error("Re-definition of module `%s'.\n", nl->Owner()->Name());
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if (inst->Type() == PRIM_AND) {
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module->addAndGate(RTLIL::escape_id(inst->Name()), net_map.at(inst->GetInput1()), net_map.at(inst->GetInput2()), net_map.at(inst->GetOutput()));
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return true;
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}
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if (inst->Type() == PRIM_OR) {
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module->addOrGate(RTLIL::escape_id(inst->Name()), net_map.at(inst->GetInput1()), net_map.at(inst->GetInput2()), net_map.at(inst->GetOutput()));
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return true;
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}
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if (inst->Type() == PRIM_XOR) {
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module->addXorGate(RTLIL::escape_id(inst->Name()), net_map.at(inst->GetInput1()), net_map.at(inst->GetInput2()), net_map.at(inst->GetOutput()));
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return true;
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}
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if (inst->Type() == PRIM_INV) {
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module->addInvGate(RTLIL::escape_id(inst->Name()), net_map.at(inst->GetInput()), net_map.at(inst->GetOutput()));
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return true;
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}
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if (inst->Type() == PRIM_MUX) {
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module->addMuxGate(RTLIL::escape_id(inst->Name()), net_map.at(inst->GetInput1()), net_map.at(inst->GetInput2()), net_map.at(inst->GetControl()), net_map.at(inst->GetOutput()));
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return true;
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}
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if (inst->Type() == PRIM_FADD)
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{
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RTLIL::SigSpec a_plus_b = module->new_wire(2, NEW_ID);
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RTLIL::SigSpec y = net_map.at(inst->GetOutput());
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y.append(net_map.at(inst->GetCout()));
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module->addAdd(NEW_ID, net_map.at(inst->GetInput1()), net_map.at(inst->GetInput2()), a_plus_b);
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module->addAdd(RTLIL::escape_id(inst->Name()), a_plus_b, net_map.at(inst->GetCin()), y);
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return true;
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}
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if (inst->Type() == PRIM_DFFRS)
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{
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RTLIL::SigSpec tmp1 = module->new_wire(1, NEW_ID);
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RTLIL::SigSpec tmp2 = module->new_wire(1, NEW_ID);
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RTLIL::SigSpec d = module->new_wire(1, NEW_ID);
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module->addOr(NEW_ID, net_map.at(inst->GetInput()), net_map.at(inst->GetSet()), tmp1);
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module->addNot(NEW_ID, net_map.at(inst->GetReset()), tmp2);
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module->addAnd(NEW_ID, tmp1, tmp2, d);
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module->addDff(NEW_ID, net_map.at(inst->GetClock()), d, net_map.at(inst->GetOutput()));
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return true;
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}
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return false;
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}
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static bool import_netlist_instance_cells(RTLIL::Module *module, std::map<Net*, RTLIL::SigBit> &net_map, Instance *inst)
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{
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if (inst->Type() == PRIM_AND) {
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module->addAnd(RTLIL::escape_id(inst->Name()), net_map.at(inst->GetInput1()), net_map.at(inst->GetInput2()), net_map.at(inst->GetOutput()));
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return true;
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}
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if (inst->Type() == PRIM_OR) {
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module->addOr(RTLIL::escape_id(inst->Name()), net_map.at(inst->GetInput1()), net_map.at(inst->GetInput2()), net_map.at(inst->GetOutput()));
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return true;
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}
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if (inst->Type() == PRIM_XOR) {
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module->addXor(RTLIL::escape_id(inst->Name()), net_map.at(inst->GetInput1()), net_map.at(inst->GetInput2()), net_map.at(inst->GetOutput()));
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return true;
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}
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if (inst->Type() == PRIM_XNOR) {
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module->addXnor(RTLIL::escape_id(inst->Name()), net_map.at(inst->GetInput1()), net_map.at(inst->GetInput2()), net_map.at(inst->GetOutput()));
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return true;
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}
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if (inst->Type() == PRIM_INV) {
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module->addNot(RTLIL::escape_id(inst->Name()), net_map.at(inst->GetInput()), net_map.at(inst->GetOutput()));
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return true;
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}
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if (inst->Type() == PRIM_MUX) {
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module->addMux(RTLIL::escape_id(inst->Name()), net_map.at(inst->GetInput1()), net_map.at(inst->GetInput2()), net_map.at(inst->GetControl()), net_map.at(inst->GetOutput()));
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return true;
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}
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if (inst->Type() == PRIM_FADD)
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{
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RTLIL::SigSpec a_plus_b = module->new_wire(2, NEW_ID);
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RTLIL::SigSpec y = net_map.at(inst->GetOutput());
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y.append(net_map.at(inst->GetCout()));
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module->addAdd(NEW_ID, net_map.at(inst->GetInput1()), net_map.at(inst->GetInput2()), a_plus_b);
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module->addAdd(RTLIL::escape_id(inst->Name()), a_plus_b, net_map.at(inst->GetCin()), y);
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return true;
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}
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if (inst->Type() == PRIM_DFFRS)
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{
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RTLIL::SigSpec tmp1 = module->new_wire(1, NEW_ID);
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RTLIL::SigSpec tmp2 = module->new_wire(1, NEW_ID);
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RTLIL::SigSpec d = module->new_wire(1, NEW_ID);
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module->addOr(NEW_ID, net_map.at(inst->GetInput()), net_map.at(inst->GetSet()), tmp1);
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module->addNot(NEW_ID, net_map.at(inst->GetReset()), tmp2);
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module->addAnd(NEW_ID, tmp1, tmp2, d);
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module->addDff(NEW_ID, net_map.at(inst->GetClock()), d, net_map.at(inst->GetOutput()));
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return true;
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}
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#define IN operatorInput(inst, net_map)
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#define IN1 operatorInput1(inst, net_map)
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#define IN2 operatorInput2(inst, net_map)
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#define OUT operatorOutput(inst, net_map, module)
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#define SIGNED inst->View()->IsSigned()
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#if 0
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if (inst->Type() == OPER_ADDER) {
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module->addAdd(RTLIL::escape_id(inst->Name()), IN1, IN2, OUT, SIGNED);
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return true;
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}
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if (inst->Type() == OPER_MULTIPLIER) {
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module->addMul(RTLIL::escape_id(inst->Name()), IN1, IN2, OUT, SIGNED);
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return true;
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}
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if (inst->Type() == OPER_DIVIDER) {
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module->addDiv(RTLIL::escape_id(inst->Name()), IN1, IN2, OUT, SIGNED);
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return true;
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}
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if (inst->Type() == OPER_MODULO) {
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module->addMod(RTLIL::escape_id(inst->Name()), IN1, IN2, OUT, SIGNED);
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return true;
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}
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if (inst->Type() == OPER_REMAINDER) {
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module->addMod(RTLIL::escape_id(inst->Name()), IN1, IN2, OUT, SIGNED);
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return true;
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}
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if (inst->Type() == OPER_SHIFT_LEFT) {
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module->addShl(RTLIL::escape_id(inst->Name()), IN1, IN2, OUT, SIGNED);
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return true;
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}
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if (inst->Type() == OPER_SHIFT_RIGHT) {
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module->addShr(RTLIL::escape_id(inst->Name()), IN1, IN2, OUT, SIGNED);
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return true;
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}
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if (inst->Type() == OPER_REDUCE_AND) {
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module->addReduceAnd(RTLIL::escape_id(inst->Name()), IN, OUT, SIGNED);
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return true;
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}
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if (inst->Type() == OPER_REDUCE_OR) {
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module->addReduceOr(RTLIL::escape_id(inst->Name()), IN, OUT, SIGNED);
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return true;
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}
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if (inst->Type() == OPER_REDUCE_XOR) {
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module->addReduceXor(RTLIL::escape_id(inst->Name()), IN, OUT, SIGNED);
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return true;
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}
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if (inst->Type() == OPER_REDUCE_NAND) {
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RTLIL::SigSpec tmp = module->new_wire(inst->OutputSize(), NEW_ID);
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module->addReduceAnd(NEW_ID, IN, tmp, SIGNED);
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module->addNot(RTLIL::escape_id(inst->Name()), tmp, OUT);
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return true;
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}
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if (inst->Type() == OPER_REDUCE_NOR) {
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RTLIL::SigSpec tmp = module->new_wire(inst->OutputSize(), NEW_ID);
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module->addReduceOr(NEW_ID, IN, tmp, SIGNED);
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module->addNot(RTLIL::escape_id(inst->Name()), tmp, OUT);
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return true;
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}
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if (inst->Type() == OPER_REDUCE_XNOR) {
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module->addReduceXnor(RTLIL::escape_id(inst->Name()), IN, OUT, SIGNED);
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return true;
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}
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if (inst->Type() == OPER_LESSTHAN) {
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module->addLt(RTLIL::escape_id(inst->Name()), IN1, IN2, OUT, SIGNED);
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return true;
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}
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if (inst->Type() == OPER_WIDE_AND) {
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module->addAnd(RTLIL::escape_id(inst->Name()), IN1, IN2, OUT, SIGNED);
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return true;
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}
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if (inst->Type() == OPER_WIDE_OR) {
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module->addOr(RTLIL::escape_id(inst->Name()), IN1, IN2, OUT, SIGNED);
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return true;
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}
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if (inst->Type() == OPER_WIDE_XOR) {
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module->addXor(RTLIL::escape_id(inst->Name()), IN1, IN2, OUT, SIGNED);
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return true;
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}
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if (inst->Type() == OPER_WIDE_NAND) {
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RTLIL::SigSpec tmp1 = module->new_wire(inst->OutputSize(), NEW_ID);
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module->addAnd(NEW_ID, IN1, IN2, tmp1, SIGNED);
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module->addNot(RTLIL::escape_id(inst->Name()), tmp1, OUT, SIGNED);
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return true;
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}
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if (inst->Type() == OPER_WIDE_NOR) {
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RTLIL::SigSpec tmp1 = module->new_wire(inst->OutputSize(), NEW_ID);
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module->addOr(NEW_ID, IN1, IN2, tmp1, SIGNED);
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module->addNot(RTLIL::escape_id(inst->Name()), tmp1, OUT, SIGNED);
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return true;
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}
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if (inst->Type() == OPER_WIDE_XNOR) {
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module->addXnor(RTLIL::escape_id(inst->Name()), IN1, IN2, OUT, SIGNED);
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return true;
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}
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if (inst->Type() == OPER_WIDE_BUF) {
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module->addPos(RTLIL::escape_id(inst->Name()), IN, OUT, SIGNED);
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return true;
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}
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if (inst->Type() == OPER_WIDE_INV) {
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module->addNot(RTLIL::escape_id(inst->Name()), IN, OUT, SIGNED);
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return true;
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}
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if (inst->Type() == OPER_MINUS) {
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module->addSub(RTLIL::escape_id(inst->Name()), IN1, IN2, OUT, SIGNED);
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return true;
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}
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if (inst->Type() == OPER_UMINUS) {
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module->addNeg(RTLIL::escape_id(inst->Name()), IN, OUT, SIGNED);
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return true;
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}
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if (inst->Type() == OPER_EQUAL) {
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module->addEq(RTLIL::escape_id(inst->Name()), IN1, IN2, OUT, SIGNED);
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return true;
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}
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if (inst->Type() == OPER_NEQUAL) {
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module->addNe(RTLIL::escape_id(inst->Name()), IN1, IN2, OUT, SIGNED);
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return true;
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}
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if (inst->Type() == OPER_WIDE_MUX) {
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module->addMux(RTLIL::escape_id(inst->Name()), IN1, IN2, net_map.at(inst->GetControl()), OUT);
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return true;
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}
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#endif
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#undef IN
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#undef IN1
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#undef IN2
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#undef OUT
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#undef SIGNED
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return false;
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}
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static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*> &nl_todo, bool mode_gates)
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{
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std::string module_name = nl->IsOperator() ? std::string("$verific$") + nl->Owner()->Name() : RTLIL::escape_id(nl->Owner()->Name());
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if (design->modules.count(module_name)) {
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if (!nl->IsOperator())
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log_cmd_error("Re-definition of module `%s'.\n", nl->Owner()->Name());
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return;
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}
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RTLIL::Module *module = new RTLIL::Module;
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module->name = RTLIL::escape_id(nl->Owner()->Name());
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module->name = module_name;
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design->modules[module->name] = module;
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log("Importing module %s.\n", RTLIL::id2cstr(module->name));
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@ -297,217 +578,15 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
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continue;
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}
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if (inst->Type() == PRIM_AND) {
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module->addAnd(RTLIL::escape_id(inst->Name()), net_map.at(inst->GetInput1()), net_map.at(inst->GetInput2()), net_map.at(inst->GetOutput()));
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continue;
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if (!mode_gates) {
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if (import_netlist_instance_cells(module, net_map, inst))
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continue;
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if (inst->IsOperator())
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log("Warning: Unsupported Verific operator: %s\n", inst->View()->Owner()->Name());
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}
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if (inst->Type() == PRIM_OR) {
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module->addOr(RTLIL::escape_id(inst->Name()), net_map.at(inst->GetInput1()), net_map.at(inst->GetInput2()), net_map.at(inst->GetOutput()));
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if (import_netlist_instance_gates(module, net_map, inst))
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continue;
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}
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if (inst->Type() == PRIM_XOR) {
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module->addXor(RTLIL::escape_id(inst->Name()), net_map.at(inst->GetInput1()), net_map.at(inst->GetInput2()), net_map.at(inst->GetOutput()));
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continue;
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}
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if (inst->Type() == PRIM_XNOR) {
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module->addXnor(RTLIL::escape_id(inst->Name()), net_map.at(inst->GetInput1()), net_map.at(inst->GetInput2()), net_map.at(inst->GetOutput()));
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continue;
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}
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if (inst->Type() == PRIM_INV) {
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module->addNot(RTLIL::escape_id(inst->Name()), net_map.at(inst->GetInput()), net_map.at(inst->GetOutput()));
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continue;
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}
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if (inst->Type() == PRIM_MUX) {
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module->addMux(RTLIL::escape_id(inst->Name()), net_map.at(inst->GetInput1()), net_map.at(inst->GetInput2()), net_map.at(inst->GetControl()), net_map.at(inst->GetOutput()));
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continue;
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}
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if (inst->Type() == PRIM_FADD)
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{
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RTLIL::SigSpec a_plus_b = module->new_wire(2, NEW_ID);
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RTLIL::SigSpec y = net_map.at(inst->GetOutput());
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y.append(net_map.at(inst->GetCout()));
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module->addAdd(NEW_ID, net_map.at(inst->GetInput1()), net_map.at(inst->GetInput2()), a_plus_b);
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module->addAdd(RTLIL::escape_id(inst->Name()), a_plus_b, net_map.at(inst->GetCin()), y);
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continue;
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}
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if (inst->Type() == PRIM_DFFRS)
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{
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RTLIL::SigSpec tmp1 = module->new_wire(1, NEW_ID);
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RTLIL::SigSpec tmp2 = module->new_wire(1, NEW_ID);
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RTLIL::SigSpec d = module->new_wire(1, NEW_ID);
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module->addOr(NEW_ID, net_map.at(inst->GetInput()), net_map.at(inst->GetSet()), tmp1);
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module->addNot(NEW_ID, net_map.at(inst->GetReset()), tmp2);
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module->addAnd(NEW_ID, tmp1, tmp2, d);
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module->addDff(NEW_ID, net_map.at(inst->GetClock()), d, net_map.at(inst->GetOutput()));
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continue;
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}
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#define IN operatorInput(inst, net_map)
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#define IN1 operatorInput1(inst, net_map)
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#define IN2 operatorInput2(inst, net_map)
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#define OUT operatorOutput(inst, net_map, module)
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#define SIGNED inst->View()->IsSigned()
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if (inst->Type() == OPER_ADDER) {
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module->addAdd(RTLIL::escape_id(inst->Name()), IN1, IN2, OUT, SIGNED);
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continue;
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}
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if (inst->Type() == OPER_MULTIPLIER) {
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module->addMul(RTLIL::escape_id(inst->Name()), IN1, IN2, OUT, SIGNED);
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continue;
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}
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if (inst->Type() == OPER_DIVIDER) {
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module->addDiv(RTLIL::escape_id(inst->Name()), IN1, IN2, OUT, SIGNED);
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continue;
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}
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if (inst->Type() == OPER_MODULO) {
|
||||
module->addMod(RTLIL::escape_id(inst->Name()), IN1, IN2, OUT, SIGNED);
|
||||
continue;
|
||||
}
|
||||
|
||||
if (inst->Type() == OPER_REMAINDER) {
|
||||
module->addMod(RTLIL::escape_id(inst->Name()), IN1, IN2, OUT, SIGNED);
|
||||
continue;
|
||||
}
|
||||
|
||||
if (inst->Type() == OPER_SHIFT_LEFT) {
|
||||
module->addShl(RTLIL::escape_id(inst->Name()), IN1, IN2, OUT, SIGNED);
|
||||
continue;
|
||||
}
|
||||
|
||||
if (inst->Type() == OPER_SHIFT_RIGHT) {
|
||||
module->addShr(RTLIL::escape_id(inst->Name()), IN1, IN2, OUT, SIGNED);
|
||||
continue;
|
||||
}
|
||||
|
||||
if (inst->Type() == OPER_REDUCE_AND) {
|
||||
module->addReduceAnd(RTLIL::escape_id(inst->Name()), IN, OUT, SIGNED);
|
||||
continue;
|
||||
}
|
||||
|
||||
if (inst->Type() == OPER_REDUCE_OR) {
|
||||
module->addReduceOr(RTLIL::escape_id(inst->Name()), IN, OUT, SIGNED);
|
||||
continue;
|
||||
}
|
||||
|
||||
if (inst->Type() == OPER_REDUCE_XOR) {
|
||||
module->addReduceXor(RTLIL::escape_id(inst->Name()), IN, OUT, SIGNED);
|
||||
continue;
|
||||
}
|
||||
|
||||
if (inst->Type() == OPER_REDUCE_NAND) {
|
||||
RTLIL::SigSpec tmp = module->new_wire(inst->OutputSize(), NEW_ID);
|
||||
module->addReduceAnd(NEW_ID, IN, tmp, SIGNED);
|
||||
module->addNot(RTLIL::escape_id(inst->Name()), tmp, OUT);
|
||||
continue;
|
||||
}
|
||||
|
||||
if (inst->Type() == OPER_REDUCE_NOR) {
|
||||
RTLIL::SigSpec tmp = module->new_wire(inst->OutputSize(), NEW_ID);
|
||||
module->addReduceOr(NEW_ID, IN, tmp, SIGNED);
|
||||
module->addNot(RTLIL::escape_id(inst->Name()), tmp, OUT);
|
||||
continue;
|
||||
}
|
||||
|
||||
if (inst->Type() == OPER_REDUCE_XNOR) {
|
||||
module->addReduceXnor(RTLIL::escape_id(inst->Name()), IN, OUT, SIGNED);
|
||||
continue;
|
||||
}
|
||||
|
||||
if (inst->Type() == OPER_LESSTHAN) {
|
||||
module->addLt(RTLIL::escape_id(inst->Name()), IN1, IN2, OUT, SIGNED);
|
||||
continue;
|
||||
}
|
||||
|
||||
if (inst->Type() == OPER_WIDE_AND) {
|
||||
module->addAnd(RTLIL::escape_id(inst->Name()), IN1, IN2, OUT, SIGNED);
|
||||
continue;
|
||||
}
|
||||
|
||||
if (inst->Type() == OPER_WIDE_OR) {
|
||||
module->addOr(RTLIL::escape_id(inst->Name()), IN1, IN2, OUT, SIGNED);
|
||||
continue;
|
||||
}
|
||||
|
||||
if (inst->Type() == OPER_WIDE_XOR) {
|
||||
module->addXor(RTLIL::escape_id(inst->Name()), IN1, IN2, OUT, SIGNED);
|
||||
continue;
|
||||
}
|
||||
|
||||
if (inst->Type() == OPER_WIDE_NAND) {
|
||||
RTLIL::SigSpec tmp1 = module->new_wire(inst->OutputSize(), NEW_ID);
|
||||
module->addAnd(NEW_ID, IN1, IN2, tmp1, SIGNED);
|
||||
module->addNot(RTLIL::escape_id(inst->Name()), tmp1, OUT, SIGNED);
|
||||
continue;
|
||||
}
|
||||
|
||||
if (inst->Type() == OPER_WIDE_NOR) {
|
||||
RTLIL::SigSpec tmp1 = module->new_wire(inst->OutputSize(), NEW_ID);
|
||||
module->addOr(NEW_ID, IN1, IN2, tmp1, SIGNED);
|
||||
module->addNot(RTLIL::escape_id(inst->Name()), tmp1, OUT, SIGNED);
|
||||
continue;
|
||||
}
|
||||
|
||||
if (inst->Type() == OPER_WIDE_XNOR) {
|
||||
module->addXnor(RTLIL::escape_id(inst->Name()), IN1, IN2, OUT, SIGNED);
|
||||
continue;
|
||||
}
|
||||
|
||||
if (inst->Type() == OPER_WIDE_BUF) {
|
||||
module->addPos(RTLIL::escape_id(inst->Name()), IN, OUT, SIGNED);
|
||||
continue;
|
||||
}
|
||||
|
||||
if (inst->Type() == OPER_WIDE_INV) {
|
||||
module->addNot(RTLIL::escape_id(inst->Name()), IN, OUT, SIGNED);
|
||||
continue;
|
||||
}
|
||||
|
||||
if (inst->Type() == OPER_MINUS) {
|
||||
module->addSub(RTLIL::escape_id(inst->Name()), IN1, IN2, OUT, SIGNED);
|
||||
continue;
|
||||
}
|
||||
|
||||
if (inst->Type() == OPER_UMINUS) {
|
||||
module->addNeg(RTLIL::escape_id(inst->Name()), IN, OUT, SIGNED);
|
||||
continue;
|
||||
}
|
||||
|
||||
if (inst->Type() == OPER_EQUAL) {
|
||||
module->addEq(RTLIL::escape_id(inst->Name()), IN1, IN2, OUT, SIGNED);
|
||||
continue;
|
||||
}
|
||||
|
||||
if (inst->Type() == OPER_NEQUAL) {
|
||||
module->addNe(RTLIL::escape_id(inst->Name()), IN1, IN2, OUT, SIGNED);
|
||||
continue;
|
||||
}
|
||||
|
||||
if (inst->Type() == OPER_WIDE_MUX) {
|
||||
module->addMux(RTLIL::escape_id(inst->Name()), IN1, IN2, net_map.at(inst->GetControl()), OUT);
|
||||
continue;
|
||||
}
|
||||
|
||||
#undef IN
|
||||
#undef IN1
|
||||
#undef IN2
|
||||
#undef OUT
|
||||
#undef SIGNED
|
||||
|
||||
if (inst->IsOperator())
|
||||
log("Warning: Unsupported Verific operator: %s\n", inst->View()->Owner()->Name());
|
||||
|
||||
if (inst->IsPrimitive())
|
||||
log_error("Unsupported Verific primitive: %s\n", inst->View()->Owner()->Name());
|
||||
|
|
@ -516,7 +595,7 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
|
|||
|
||||
RTLIL::Cell *cell = new RTLIL::Cell;
|
||||
cell->name = RTLIL::escape_id(inst->Name());
|
||||
cell->type = RTLIL::escape_id(inst->View()->Owner()->Name());
|
||||
cell->type = inst->IsOperator() ? std::string("$verific$") + inst->View()->Owner()->Name() : RTLIL::escape_id(inst->View()->Owner()->Name());
|
||||
module->add(cell);
|
||||
|
||||
PortRef *pr ;
|
||||
|
|
@ -555,11 +634,11 @@ struct VerificPass : public Pass {
|
|||
log("Load the specified VHDL files into Verific.\n");
|
||||
log("\n");
|
||||
log("\n");
|
||||
log(" verific -import <top-module>..\n");
|
||||
log(" verific -import [-gates] {-all | <top-module>..}\n");
|
||||
log("\n");
|
||||
log("Elaborate the design for the sepcified top modules, import to Yosys and\n");
|
||||
log("reset the internal state of Verific.\n");
|
||||
log("\n");
|
||||
log("reset the internal state of Verific. A gate-level netlist is created\n");
|
||||
log("when called with -gates.\n");
|
||||
log("\n");
|
||||
log("Visit http://verific.com/ for more information on Verific.\n");
|
||||
log("\n");
|
||||
|
|
@ -642,11 +721,48 @@ struct VerificPass : public Pass {
|
|||
if (args.size() > 1 && args[1] == "-import")
|
||||
{
|
||||
std::set<Netlist*> nl_todo, nl_done;
|
||||
bool mode_all = false, mode_gates = false;
|
||||
|
||||
if (args.size() == 2)
|
||||
log_cmd_error("No top module specified.\n");
|
||||
size_t argidx = 2;
|
||||
for (; argidx < args.size(); argidx++) {
|
||||
if (args[argidx] == "-all") {
|
||||
mode_all = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-gates") {
|
||||
mode_gates = true;
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
for (size_t argidx = 2; argidx < args.size(); argidx++) {
|
||||
if (argidx > args.size() && args[argidx].substr(0, 1) == "-")
|
||||
cmd_error(args, argidx, "unkown option");
|
||||
|
||||
if (mode_all)
|
||||
{
|
||||
if (argidx != args.size())
|
||||
log_cmd_error("Got -all and an explicit list of top modules.\n");
|
||||
|
||||
MapIter m1, m2, m3;
|
||||
VeriModule *mod;
|
||||
FOREACH_VERILOG_MODULE(m1, mod)
|
||||
args.push_back(mod->Name());
|
||||
|
||||
VhdlLibrary *lib;
|
||||
VhdlPrimaryUnit *primunit;
|
||||
FOREACH_VHDL_LIBRARY(m1, lib)
|
||||
FOREACH_VHDL_PRIMARY_UNIT(lib, m2, primunit) {
|
||||
if (primunit->IsPackageDecl())
|
||||
continue;
|
||||
args.push_back(primunit->Name());
|
||||
}
|
||||
}
|
||||
else
|
||||
if (argidx == args.size())
|
||||
log_cmd_error("No top module specified.\n");
|
||||
|
||||
for (; argidx < args.size(); argidx++) {
|
||||
if (veri_file::GetModule(args[argidx].c_str())) {
|
||||
if (!veri_file::Elaborate(args[argidx].c_str()))
|
||||
log_cmd_error("Elaboration of top module `%s' failed.\n", args[argidx].c_str());
|
||||
|
|
@ -661,7 +777,7 @@ struct VerificPass : public Pass {
|
|||
while (!nl_todo.empty()) {
|
||||
Netlist *nl = *nl_todo.begin();
|
||||
if (nl_done.count(nl) == 0)
|
||||
import_netlist(design, nl, nl_todo);
|
||||
import_netlist(design, nl, nl_todo, mode_gates);
|
||||
nl_todo.erase(nl);
|
||||
nl_done.insert(nl);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -718,7 +718,7 @@ void RTLIL::Module::check()
|
|||
for (auto &it2 : it.second->parameters) {
|
||||
assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
|
||||
}
|
||||
if (it.second->type[0] == '$' && it.second->type.substr(0, 3) != "$__" && it.second->type.substr(0, 8) != "$paramod") {
|
||||
if (it.second->type[0] == '$' && it.second->type.substr(0, 3) != "$__" && it.second->type.substr(0, 8) != "$paramod" && it.second->type.substr(0, 9) != "$verific$") {
|
||||
InternalCellChecker checker(this, it.second);
|
||||
checker.check();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -101,7 +101,7 @@ do
|
|||
|
||||
test_count=0
|
||||
test_passes() {
|
||||
"$toolsdir"/../../yosys -b "verilog $backend_opts" "$@" -o ${bn}_syn${test_count}.v $fn $scriptfiles
|
||||
"$toolsdir"/../../yosys -b "verilog $backend_opts" -o ${bn}_syn${test_count}.v "$@"
|
||||
compile_and_run ${bn}_tb_syn${test_count} ${bn}_out_syn${test_count} \
|
||||
${bn}_tb.v ${bn}_syn${test_count}.v $libs \
|
||||
"$toolsdir"/../../techlibs/common/simlib.v \
|
||||
|
|
@ -112,12 +112,16 @@ do
|
|||
}
|
||||
|
||||
if [ -n "$scriptfiles" ]; then
|
||||
test_passes
|
||||
test_passes $fn $scriptfiles
|
||||
elif [ -n "$scriptopt" ]; then
|
||||
test_passes -f "$frontend" -p "$scriptopt"
|
||||
test_passes -f "$frontend" -p "$scriptopt" $fn
|
||||
elif [ "$frontend" = "verific" ]; then
|
||||
test_passes -p "verific -vlog2k $fn; verific -import -all; opt; memory;;"
|
||||
elif [ "$frontend" = "verific_gates" ]; then
|
||||
test_passes -p "verific -vlog2k $fn; verific -import -gates -all; opt; memory;;"
|
||||
else
|
||||
test_passes -f "$frontend" -p "hierarchy; proc; opt; memory; opt; fsm; opt"
|
||||
test_passes -f "$frontend" -p "hierarchy; proc; opt; memory; opt; fsm; opt; techmap; opt; abc -dff; opt"
|
||||
test_passes -f "$frontend" -p "hierarchy; proc; opt; memory; opt; fsm; opt" $fn
|
||||
test_passes -f "$frontend" -p "hierarchy; proc; opt; memory; opt; fsm; opt; techmap; opt; abc -dff; opt" $fn
|
||||
fi
|
||||
touch ../${bn}.log
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue