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write_xaiger to not use module POs but only write outputs if driven

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This commit is contained in:
Eddie Hung 2019-11-21 16:19:28 -08:00
parent c4ec42ac38
commit 0ab1e496dc
1 changed files with 22 additions and 10 deletions
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32
backends/aiger/xaiger.cc
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@ -542,18 +542,30 @@ struct XAigerWriter
} }
for (auto bit : unused_bits) for (auto bit : unused_bits)
undriven_bits.erase(bit); if (holes_mode)
undriven_bits.erase(bit);
else if (!undriven_bits.count(bit))
output_bits.insert(bit);
if (!undriven_bits.empty() && !holes_mode) { if (!holes_mode) {
bool whole_module = module->design->selected_whole_module(module->name); for (auto port : module->ports) {
undriven_bits.sort(); auto wire = module->wire(port);
for (auto bit : undriven_bits) { if (!wire->port_output)
if (whole_module) continue;
log_warning("Treating undriven bit %s.%s like $anyseq.\n", log_id(module), log_signal(bit)); for (int i = 0; i < GetSize(wire); i++) {
input_bits.insert(bit); SigBit wirebit(wire, i);
SigBit bit = sigmap(wirebit);
if (bit == State::Sx)
continue;
if (!undriven_bits.count(bit)) {
output_bits.insert(wirebit);
}
}
} }
if (whole_module)
log_warning("Treating a total of %d undriven bits in %s like $anyseq.\n", GetSize(undriven_bits), log_id(module)); if (!undriven_bits.empty())
for (auto bit : undriven_bits)
input_bits.insert(bit);
} }
if (holes_mode) { if (holes_mode) {