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Add clean_zerowidth pass, use it for Verilog output.

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This should remove instances of zero-width sigspecs in the netlist,
avoiding problems in the Verilog backend with emitting them.

See #3103.
This commit is contained in:
Marcelina Kościelnicka 2021-12-11 16:07:29 +01:00
parent bdc6ba019c
commit 0aad88a2fb
3 changed files with 214 additions and 1 deletions
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3
passes/cmds/Makefile.inc
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@ -40,4 +40,5 @@ endif
OBJS += passes/cmds/scratchpad.o
OBJS += passes/cmds/logger.o
OBJS += passes/cmds/printattrs.o
OBJS += passes/cmds/sta.o
OBJS += passes/cmds/sta.o
OBJS += passes/cmds/clean_zerowidth.o