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Merge pull request #4605 from povik/liberty-unit-delay

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read_liberty: Optionally import unit delay arcs
This commit is contained in:
Martin Povišer 2024-10-07 16:11:51 +02:00 • committed by GitHub
commit 0aab8b4158
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4 changed files with 55 additions and 5 deletions
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46
frontends/liberty/liberty.cc
View file

@ -465,6 +465,9 @@ struct LibertyFrontend : public Frontend {
log(" -setattr <attribute_name>\n");
log(" set the specified attribute (to the value 1) on all loaded modules\n");
log("\n");
log(" -unit_delay\n");
log(" import combinational timing arcs under the unit delay model\n");
log("\n");
}
void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
{
@ -475,6 +478,7 @@ struct LibertyFrontend : public Frontend {
bool flag_ignore_miss_func = false;
bool flag_ignore_miss_dir = false;
bool flag_ignore_miss_data_latch = false;
bool flag_unit_delay = false;
std::vector<std::string> attributes;
size_t argidx;
@ -514,6 +518,10 @@ struct LibertyFrontend : public Frontend {
attributes.push_back(RTLIL::escape_id(args[++argidx]));
continue;
}
if (arg == "-unit_delay") {
flag_unit_delay = true;
continue;
}
break;
}
extra_args(f, filename, args, argidx);
@ -652,6 +660,7 @@ struct LibertyFrontend : public Frontend {
continue;
RTLIL::Wire *wire = module->wires_.at(RTLIL::escape_id(node->args.at(0)));
log_assert(wire);
if (dir && dir->value == "inout") {
wire->port_input = true;
@ -690,6 +699,43 @@ struct LibertyFrontend : public Frontend {
}
module->connect(RTLIL::SigSig(wire, out_sig));
}
if (flag_unit_delay) {
pool<Wire *> done;
for (auto timing : node->children)
if (timing->id == "timing" && timing->args.empty()) {
auto type = timing->find("timing_type");
auto related_pin = timing->find("related_pin");
if (!type || type->value != "combinational" || !related_pin)
continue;
Wire *related = module->wire(RTLIL::escape_id(related_pin->value));
if (!related)
log_error("Failed to find related pin %s for timing of pin %s on %s\n",
related_pin->value.c_str(), log_id(wire), log_id(module));
if (done.count(related))
continue;
RTLIL::Cell *spec = module->addCell(NEW_ID, ID($specify2));
spec->setParam(ID::SRC_WIDTH, 1);
spec->setParam(ID::DST_WIDTH, 1);
spec->setParam(ID::T_FALL_MAX, 1000);
spec->setParam(ID::T_FALL_TYP, 1000);
spec->setParam(ID::T_FALL_MIN, 1000);
spec->setParam(ID::T_RISE_MAX, 1000);
spec->setParam(ID::T_RISE_TYP, 1000);
spec->setParam(ID::T_RISE_MIN, 1000);
spec->setParam(ID::SRC_DST_POL, false);
spec->setParam(ID::SRC_DST_PEN, false);
spec->setParam(ID::FULL, false);
spec->setPort(ID::EN, Const(1, 1));
spec->setPort(ID::SRC, related);
spec->setPort(ID::DST, wire);
done.insert(related);
}
}
}
}

1
tests/liberty/.gitignore vendored
View file

@ -1,4 +1,3 @@
*.log
test.ys
*.filtered
*.verilogsim

10
tests/liberty/run-test.sh
View file

@ -3,11 +3,13 @@ set -e
for x in *.lib; do
echo "Testing on $x.."
echo "read_verilog small.v" > test.ys
echo "synth -top small" >> test.ys
echo "dfflibmap -info -liberty ${x}" >> test.ys
../../yosys -ql ${x%.lib}.log -s test.ys
../../yosys -p "read_verilog small.v; synth -top small; dfflibmap -info -liberty ${x}" -ql ${x%.lib}.log
../../yosys-filterlib - $x 2>/dev/null > $x.filtered
../../yosys-filterlib -verilogsim $x > $x.verilogsim
diff $x.filtered $x.filtered.ok && diff $x.verilogsim $x.verilogsim.ok
done
for x in *.ys; do
echo "Running $x.."
../../yosys -q -s $x -l ${x%.ys}.log
done

3
tests/liberty/unit_delay.ys Normal file
View file

@ -0,0 +1,3 @@
# Nothing gets imported: the file lacks timing data
read_liberty -wb -unit_delay normal.lib
select -assert-none =*/t:$specify*