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nexus: Use memory_libmap
pass.
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11 changed files with 661 additions and 501 deletions
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@ -3,7 +3,7 @@ design -save read
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# Check that we use the right dual and single clock variants
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chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 18 sync_ram_sdp
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chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp
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synth_nexus -top sync_ram_sdp
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cd sync_ram_sdp
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select -assert-count 1 t:PDPSC16K
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@ -11,7 +11,7 @@ select -assert-none t:PDPSC16K t:INV t:IB t:OB t:VLO t:VHI %% t:* %D
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design -reset
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read_verilog blockram_dc.v
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chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 18 sync_ram_sdp_dc
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chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp_dc
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synth_nexus -top sync_ram_sdp_dc
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cd sync_ram_sdp_dc
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select -assert-count 1 t:PDP16K
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