mirror of
https://github.com/YosysHQ/yosys
synced 2025-06-17 11:26:18 +00:00
nexus: Use memory_libmap
pass.
This commit is contained in:
parent
a04b025abf
commit
0a8eaca322
11 changed files with 661 additions and 501 deletions
|
@ -1,34 +1,23 @@
|
|||
module \$__NEXUS_DPR16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
|
||||
parameter [63:0] INIT = 64'b0;
|
||||
parameter CLKPOL2 = 1;
|
||||
input CLK1;
|
||||
module $__NEXUS_DPR16X4_ (...);
|
||||
parameter INIT = 64'b0;
|
||||
|
||||
input [3:0] A1ADDR;
|
||||
output [3:0] A1DATA;
|
||||
input PORT_W_CLK;
|
||||
input [3:0] PORT_W_ADDR;
|
||||
input [3:0] PORT_W_WR_DATA;
|
||||
input PORT_W_WR_EN;
|
||||
|
||||
input [3:0] B1ADDR;
|
||||
input [3:0] B1DATA;
|
||||
input B1EN;
|
||||
|
||||
|
||||
wire wck;
|
||||
|
||||
generate
|
||||
if (CLKPOL2)
|
||||
assign wck = CLK1;
|
||||
else
|
||||
INV wck_inv_i (.A(CLK1), .Z(wck));
|
||||
endgenerate
|
||||
input [3:0] PORT_R_ADDR;
|
||||
output [3:0] PORT_R_RD_DATA;
|
||||
|
||||
DPR16X4 #(
|
||||
.INITVAL($sformatf("0x%08x", INIT))
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.RAD(A1ADDR),
|
||||
.DO(A1DATA),
|
||||
.RAD(PORT_R_ADDR),
|
||||
.DO(PORT_R_RD_DATA),
|
||||
|
||||
.WAD(B1ADDR),
|
||||
.DI(B1DATA),
|
||||
.WCK(CLK1),
|
||||
.WRE(B1EN)
|
||||
.WAD(PORT_W_ADDR),
|
||||
.DI(PORT_W_WR_DATA),
|
||||
.WCK(PORT_W_CLK),
|
||||
.WRE(PORT_W_WR_EN)
|
||||
);
|
||||
endmodule
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue