mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-24 01:25:33 +00:00
synth_gatemate: Apply review remarks
* remove unused techmap models in `map_regs.v` * replace RAM initilization loops with 320-bit-writes * add script to test targets in top-level Makefile * remove `MAXWIDTH` parameter and treat both vector widths individually in `mult_map.v` * iterate over all modules in `gatemate_bramopt` pass
This commit is contained in:
parent
cfcc38582a
commit
0a72952d5f
6 changed files with 212 additions and 279 deletions
1
Makefile
1
Makefile
|
@ -814,6 +814,7 @@ test: $(TARGETS) $(EXTRA_TARGETS)
|
|||
+cd tests/arch/intel_alm && bash run-test.sh $(SEEDOPT)
|
||||
+cd tests/arch/nexus && bash run-test.sh $(SEEDOPT)
|
||||
+cd tests/arch/quicklogic && bash run-test.sh $(SEEDOPT)
|
||||
+cd tests/arch/gatemate && bash run-test.sh $(SEEDOPT)
|
||||
+cd tests/rpc && bash run-test.sh
|
||||
+cd tests/memfile && bash run-test.sh
|
||||
+cd tests/verilog && bash run-test.sh
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue