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Fix warnings

This commit is contained in:
Eddie Hung 2019-06-06 14:01:42 -07:00
parent ccdf989025
commit 0a66720f6f
2 changed files with 3 additions and 3 deletions

View file

@ -74,7 +74,7 @@ always @*
else o <= {W{1'bx}}; else o <= {W{1'bx}};
endmodule endmodule
module mux_if_unbal_5_3_nonexcl #(parameter N=4, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); module mux_if_unbal_5_3_nonexcl #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
always @* begin always @* begin
o <= {W{1'bx}}; o <= {W{1'bx}};
if (s == 0) o <= i[0*W+:W]; if (s == 0) o <= i[0*W+:W];
@ -86,7 +86,7 @@ always @* begin
end end
endmodule endmodule
module mux_case_unbal_7_7#(parameter N=7, parameter W=7) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); module mux_case_unbal_8_7#(parameter N=8, parameter W=7) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
always @* begin always @* begin
o <= {W{1'bx}}; o <= {W{1'bx}};
case (s) case (s)

View file

@ -120,7 +120,7 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter sat -verify -prove-asserts -show-ports miter
design -load read design -load read
hierarchy -top mux_case_unbal_7_7 hierarchy -top mux_case_unbal_8_7
prep prep
design -save gold design -save gold
muxpack muxpack