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Fix translation bug: The old code really checks for the presense of a node, not an edge in glift and flatten.

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Add back statement that inserts nodes in order in opt_expr.cc.
This commit is contained in:
Rasmus Munk Larsen 2023-10-05 17:01:42 -07:00
parent fd7bd420b3
commit 0a37c2a301
4 changed files with 4 additions and 9 deletions
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8
kernel/utils.h
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@ -174,11 +174,7 @@ template <typename T, typename C = std::less<T>, typename OPS = hash_ops<T>> cla
void edge(T left, T right) { edge(node(left), node(right)); } void edge(T left, T right) { edge(node(left), node(right)); }
bool has_edges(const T &node) bool has_node(const T &node) { return node_to_index.find(node) != node_to_index.end(); }
{
auto it = node_to_index.find(node);
return it == node_to_index.end() || !edges[it->second].empty();
}
bool sort() bool sort()
{ {
@ -192,8 +188,6 @@ template <typename T, typename C = std::less<T>, typename OPS = hash_ops<T>> cla
std::vector<bool> marked_cells(edges.size(), false); std::vector<bool> marked_cells(edges.size(), false);
std::vector<bool> active_cells(edges.size(), false); std::vector<bool> active_cells(edges.size(), false);
std::vector<int> active_stack; std::vector<int> active_stack;
marked_cells.reserve(edges.size());
sorted.reserve(edges.size()); sorted.reserve(edges.size());
for (const auto &it : node_to_index) for (const auto &it : node_to_index)

2
passes/cmds/glift.cc
View file

@ -582,7 +582,7 @@ struct GliftPass : public Pass {
for (auto cell : module->selected_cells()) { for (auto cell : module->selected_cells()) {
RTLIL::Module *tpl = design->module(cell->type); RTLIL::Module *tpl = design->module(cell->type);
if (tpl != nullptr) { if (tpl != nullptr) {
if (!topo_modules.has_edges(tpl)) if (!topo_modules.has_node(tpl))
worklist.push_back(tpl); worklist.push_back(tpl);
topo_modules.edge(tpl, module); topo_modules.edge(tpl, module);
non_top_modules.insert(cell->type); non_top_modules.insert(cell->type);

1
passes/opt/opt_expr.cc
View file

@ -424,6 +424,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
for (auto &bit : sig) for (auto &bit : sig)
outbit_to_cell[bit].insert(cell); outbit_to_cell[bit].insert(cell);
} }
cells.node(cell);
} }
// Build the graph for the topological sort. // Build the graph for the topological sort.

2
passes/techmap/flatten.cc
View file

@ -312,7 +312,7 @@ struct FlattenPass : public Pass {
for (auto cell : module->selected_cells()) { for (auto cell : module->selected_cells()) {
RTLIL::Module *tpl = design->module(cell->type); RTLIL::Module *tpl = design->module(cell->type);
if (tpl != nullptr) { if (tpl != nullptr) {
if (!topo_modules.has_edges(tpl)) if (!topo_modules.has_node(tpl))
worklist.insert(tpl); worklist.insert(tpl);
topo_modules.edge(tpl, module); topo_modules.edge(tpl, module);
} }