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Moved equiv stuff to passes/equiv/
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Clifford Wolf
parent
abf8398216
commit
0a225f8b27
5 changed files with 5 additions and 3 deletions
253
passes/equiv/equiv_simple.cc
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253
passes/equiv/equiv_simple.cc
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/satgen.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct EquivSimpleWorker
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{
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Module *module;
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Cell *equiv_cell;
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SigMap &sigmap;
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dict<SigBit, Cell*> &bit2driver;
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ezDefaultSAT ez;
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SatGen satgen;
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int max_seq;
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EquivSimpleWorker(Cell *equiv_cell, SigMap &sigmap, dict<SigBit, Cell*> &bit2driver, int max_seq) :
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module(equiv_cell->module), equiv_cell(equiv_cell), sigmap(sigmap),
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bit2driver(bit2driver), satgen(&ez, &sigmap), max_seq(max_seq)
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{
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}
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void find_input_cone(pool<SigBit> &next_seed, pool<Cell*> &cells_cone, pool<SigBit> &bits_cone, const pool<Cell*> &cells_stop, const pool<SigBit> &bits_stop, Cell *cell)
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{
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if (cells_cone.count(cell))
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return;
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cells_cone.insert(cell);
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if (cells_stop.count(cell))
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return;
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for (auto &conn : cell->connections())
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if (yosys_celltypes.cell_input(cell->type, conn.first))
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for (auto bit : sigmap(conn.second)) {
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if (cell->type.in("$dff", "$_DFF_P_", "$_DFF_N_")) {
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if (!conn.first.in("\\CLK", "\\C"))
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next_seed.insert(bit);
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} else
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find_input_cone(next_seed, cells_cone, bits_cone, cells_stop, bits_stop, bit);
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}
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}
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void find_input_cone(pool<SigBit> &next_seed, pool<Cell*> &cells_cone, pool<SigBit> &bits_cone, const pool<Cell*> &cells_stop, const pool<SigBit> &bits_stop, SigBit bit)
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{
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if (bits_cone.count(bit))
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return;
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bits_cone.insert(bit);
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if (bits_stop.count(bit))
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return;
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if (!bit2driver.count(bit))
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return;
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find_input_cone(next_seed, cells_cone, bits_cone, cells_stop, bits_stop, bit2driver.at(bit));
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}
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bool run()
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{
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SigBit bit_a = sigmap(equiv_cell->getPort("\\A")).to_single_sigbit();
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SigBit bit_b = sigmap(equiv_cell->getPort("\\B")).to_single_sigbit();
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int ez_a = satgen.importSigBit(bit_a, max_seq+1);
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int ez_b = satgen.importSigBit(bit_b, max_seq+1);
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ez.assume(ez.XOR(ez_a, ez_b));
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pool<SigBit> seed_a = { bit_a };
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pool<SigBit> seed_b = { bit_b };
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log(" Trying to prove $equiv cell %s:\n", log_id(equiv_cell));
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log(" A = %s, B = %s, Y = %s\n", log_signal(bit_a), log_signal(bit_b), log_signal(equiv_cell->getPort("\\Y")));
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int step = max_seq;
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while (1)
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{
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pool<Cell*> no_stop_cells;
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pool<SigBit> no_stop_bits;
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pool<Cell*> full_cells_cone_a, full_cells_cone_b;
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pool<SigBit> full_bits_cone_a, full_bits_cone_b;
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pool<SigBit> next_seed_a, next_seed_b;
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for (auto bit_a : seed_a)
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find_input_cone(next_seed_a, full_cells_cone_a, full_bits_cone_a, no_stop_cells, no_stop_bits, bit_a);
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next_seed_a.clear();
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for (auto bit_b : seed_b)
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find_input_cone(next_seed_b, full_cells_cone_b, full_bits_cone_b, no_stop_cells, no_stop_bits, bit_b);
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next_seed_b.clear();
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pool<Cell*> short_cells_cone_a, short_cells_cone_b;
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pool<SigBit> short_bits_cone_a, short_bits_cone_b;
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for (auto bit_a : seed_a)
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find_input_cone(next_seed_a, short_cells_cone_a, short_bits_cone_a, full_cells_cone_b, full_bits_cone_b, bit_a);
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next_seed_a.swap(seed_a);
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for (auto bit_b : seed_b)
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find_input_cone(next_seed_b, short_cells_cone_b, short_bits_cone_b, full_cells_cone_a, full_bits_cone_a, bit_b);
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next_seed_b.swap(seed_b);
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pool<Cell*> problem_cells;
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problem_cells.insert(short_cells_cone_a.begin(), short_cells_cone_a.end());
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problem_cells.insert(short_cells_cone_b.begin(), short_cells_cone_b.end());
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log(" Adding %d new cells to the problem (%d A, %d B, %d shared).\n",
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GetSize(problem_cells), GetSize(short_cells_cone_a), GetSize(short_cells_cone_b),
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(GetSize(short_cells_cone_a) + GetSize(short_cells_cone_b)) - GetSize(problem_cells));
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for (auto cell : problem_cells)
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satgen.importCell(cell, step+1);
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log(" Problem size at t=%d: %d literals, %d clauses\n", step, ez.numCnfVariables(), ez.numCnfClauses());
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if (!ez.solve()) {
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log(" Proved equivalence! Marking $equiv cell as proven.\n");
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equiv_cell->setPort("\\B", equiv_cell->getPort("\\A"));
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return true;
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}
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log(" Failed to prove equivalence with sequence length %d.\n", max_seq - step);
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if (--step < 0) {
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log(" Reached sequence limit.\n");
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break;
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}
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if (seed_a.empty() && seed_b.empty()) {
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log(" No nets to continue in previous time step.\n");
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break;
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}
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if (seed_a.empty()) {
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log(" No nets on A-side to continue in previous time step.\n");
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break;
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}
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if (seed_b.empty()) {
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log(" No nets on B-side to continue in previous time step.\n");
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break;
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}
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#if 0
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log(" Continuing analysis in previous time step with the following nets:\n");
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for (auto bit : seed_a)
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log(" A: %s\n", log_signal(bit));
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for (auto bit : seed_b)
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log(" B: %s\n", log_signal(bit));
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#else
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log(" Continuing analysis in previous time step with %d A- and %d B-nets.\n", GetSize(seed_a), GetSize(seed_b));
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#endif
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}
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return false;
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}
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};
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struct EquivSimplePass : public Pass {
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EquivSimplePass() : Pass("equiv_simple", "try proving simple $equiv instances") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" equiv_simple [options] [selection]\n");
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log("\n");
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log("This command tries to prove $equiv cells using a simple direct SAT approach.\n");
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log("\n");
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log(" -seq <N>\n");
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log(" the max. number of time steps to be considered (default = 1)\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, Design *design)
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{
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int success_counter = 0;
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int max_seq = 1;
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log_header("Executing EQUIV_SIMPLE pass.\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-seq" && argidx+1 < args.size()) {
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max_seq = atoi(args[++argidx].c_str());
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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CellTypes ct;
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ct.setup_internals();
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ct.setup_stdcells();
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for (auto module : design->selected_modules())
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{
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vector<Cell*> unproven_equiv_cells;
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for (auto cell : module->selected_cells())
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if (cell->type == "$equiv" && cell->getPort("\\A") != cell->getPort("\\B"))
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unproven_equiv_cells.push_back(cell);
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if (unproven_equiv_cells.empty())
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continue;
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log("Found %d unproven $equiv cells in %s:\n", GetSize(unproven_equiv_cells), log_id(module));
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SigMap sigmap(module);
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dict<SigBit, Cell*> bit2driver;
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for (auto cell : module->cells()) {
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if (!ct.cell_known(cell->type) && !cell->type.in("$dff", "$_DFF_P_", "$_DFF_N_"))
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continue;
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for (auto &conn : cell->connections())
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if (yosys_celltypes.cell_output(cell->type, conn.first))
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for (auto bit : sigmap(conn.second))
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bit2driver[bit] = cell;
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}
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for (auto cell : unproven_equiv_cells) {
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EquivSimpleWorker worker(cell, sigmap, bit2driver, max_seq);
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if (worker.run())
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success_counter++;
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}
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}
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log("Proved %d previously unproven $equiv cells.\n", success_counter);
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}
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} EquivSimplePass;
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PRIVATE_NAMESPACE_END
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