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Merge pull request #2029 from whitequark/fix-simplify-memory-sv_logic

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ast/simplify: don't bitblast async ROMs declared as `logic`
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clairexen 2020-05-29 16:52:11 +02:00 • committed by GitHub
commit 0a14e1e837
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3 changed files with 11 additions and 2 deletions
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4
frontends/ast/simplify.cc
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@ -3540,8 +3540,8 @@ void AstNode::mem2reg_as_needed_pass1(dict<AstNode*, pool<std::string>> &mem2reg
} }
} }
// also activate if requested, either by using mem2reg attribute or by declaring array as 'wire' instead of 'reg' // also activate if requested, either by using mem2reg attribute or by declaring array as 'wire' instead of 'reg' or 'logic'
if (type == AST_MEMORY && (get_bool_attribute(ID::mem2reg) || (flags & AstNode::MEM2REG_FL_ALL) || !is_reg)) if (type == AST_MEMORY && (get_bool_attribute(ID::mem2reg) || (flags & AstNode::MEM2REG_FL_ALL) || !(is_reg || is_logic)))
mem2reg_candidates[this] |= AstNode::MEM2REG_FL_FORCED; mem2reg_candidates[this] |= AstNode::MEM2REG_FL_FORCED;
if (type == AST_MODULE && get_bool_attribute(ID::mem2reg)) if (type == AST_MODULE && get_bool_attribute(ID::mem2reg))

6
tests/svtypes/logic_rom.sv Normal file
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@ -0,0 +1,6 @@
module top(input [3:0] addr, output [7:0] data);
logic [7:0] mem[0:15];
assign data = mem[addr];
integer i;
initial for(i = 0; i < 16; i = i + 1) mem[i] = i;
endmodule

3
tests/svtypes/logic_rom.ys Normal file
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@ -0,0 +1,3 @@
read_verilog -sv logic_rom.sv
prep -top top
select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=8 %i