mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-31 19:52:31 +00:00
Merge remote-tracking branch 'origin/master' into xaig_dff
This commit is contained in:
Eddie Hung
commit
09ee96e8c2
228 changed files with 35110 additions and 24029 deletions
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@ -38,6 +38,17 @@ module IBUF(
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assign O = I;
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endmodule
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module IBUFG(
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output O,
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(* iopad_external_pin *)
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input I);
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parameter CAPACITANCE = "DONT_CARE";
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parameter IBUF_DELAY_VALUE = "0";
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parameter IBUF_LOW_PWR = "TRUE";
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parameter IOSTANDARD = "DEFAULT";
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assign O = I;
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endmodule
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module OBUF(
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(* iopad_external_pin *)
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output O,
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@ -578,6 +589,515 @@ module SRLC32E (
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endgenerate
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endmodule
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// DSP
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// Virtex 2, Virtex 2 Pro, Spartan 3.
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// Asynchronous mode.
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module MULT18X18 (
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input signed [17:0] A,
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input signed [17:0] B,
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output signed [35:0] P
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);
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assign P = A * B;
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endmodule
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// Synchronous mode.
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module MULT18X18S (
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input signed [17:0] A,
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input signed [17:0] B,
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output reg signed [35:0] P,
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(* clkbuf_sink *)
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input C,
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input CE,
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input R
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);
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always @(posedge C)
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if (R)
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P <= 0;
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else if (CE)
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P <= A * B;
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endmodule
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// Spartan 3E, Spartan 3A.
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module MULT18X18SIO (
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input signed [17:0] A,
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input signed [17:0] B,
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output signed [35:0] P,
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(* clkbuf_sink *)
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input CLK,
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input CEA,
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input CEB,
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input CEP,
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input RSTA,
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input RSTB,
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input RSTP,
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input signed [17:0] BCIN,
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output signed [17:0] BCOUT
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);
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parameter integer AREG = 1;
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parameter integer BREG = 1;
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parameter B_INPUT = "DIRECT";
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parameter integer PREG = 1;
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// The multiplier.
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wire signed [35:0] P_MULT;
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assign P_MULT = A_MULT * B_MULT;
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// The cascade output.
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assign BCOUT = B_MULT;
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// The B input multiplexer.
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wire signed [17:0] B_MUX;
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assign B_MUX = (B_INPUT == "DIRECT") ? B : BCIN;
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// The registers.
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reg signed [17:0] A_REG;
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reg signed [17:0] B_REG;
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reg signed [35:0] P_REG;
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initial begin
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A_REG = 0;
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B_REG = 0;
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P_REG = 0;
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end
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always @(posedge CLK) begin
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if (RSTA)
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A_REG <= 0;
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else if (CEA)
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A_REG <= A;
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if (RSTB)
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B_REG <= 0;
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else if (CEB)
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B_REG <= B_MUX;
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if (RSTP)
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P_REG <= 0;
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else if (CEP)
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P_REG <= P_MULT;
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end
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// The register enables.
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wire signed [17:0] A_MULT;
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wire signed [17:0] B_MULT;
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assign A_MULT = (AREG == 1) ? A_REG : A;
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assign B_MULT = (BREG == 1) ? B_REG : B_MUX;
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assign P = (PREG == 1) ? P_REG : P_MULT;
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endmodule
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// Spartan 3A DSP.
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module DSP48A (
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input signed [17:0] A,
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input signed [17:0] B,
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input signed [47:0] C,
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input signed [17:0] D,
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input signed [47:0] PCIN,
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input CARRYIN,
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input [7:0] OPMODE,
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output signed [47:0] P,
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output signed [17:0] BCOUT,
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output signed [47:0] PCOUT,
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output CARRYOUT,
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(* clkbuf_sink *)
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input CLK,
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input CEA,
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input CEB,
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input CEC,
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input CED,
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input CEM,
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input CECARRYIN,
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input CEOPMODE,
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input CEP,
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input RSTA,
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input RSTB,
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input RSTC,
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input RSTD,
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input RSTM,
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input RSTCARRYIN,
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input RSTOPMODE,
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input RSTP
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);
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parameter integer A0REG = 0;
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parameter integer A1REG = 1;
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parameter integer B0REG = 0;
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parameter integer B1REG = 1;
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parameter integer CREG = 1;
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parameter integer DREG = 1;
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parameter integer MREG = 1;
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parameter integer CARRYINREG = 1;
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parameter integer OPMODEREG = 1;
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parameter integer PREG = 1;
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parameter CARRYINSEL = "CARRYIN";
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parameter RSTTYPE = "SYNC";
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// This is a strict subset of Spartan 6 -- reuse its model.
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DSP48A1 #(
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.A0REG(A0REG),
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.A1REG(A1REG),
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.B0REG(B0REG),
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.B1REG(B1REG),
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.CREG(CREG),
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.DREG(DREG),
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.MREG(MREG),
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.CARRYINREG(CARRYINREG),
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.CARRYOUTREG(0),
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.OPMODEREG(OPMODEREG),
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.PREG(PREG),
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.CARRYINSEL(CARRYINSEL),
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.RSTTYPE(RSTTYPE)
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) upgrade (
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.A(A),
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.B(B),
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.C(C),
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.D(D),
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.PCIN(PCIN),
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.CARRYIN(CARRYIN),
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.OPMODE(OPMODE),
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// M unconnected
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.P(P),
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.BCOUT(BCOUT),
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.PCOUT(PCOUT),
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.CARRYOUT(CARRYOUT),
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// CARRYOUTF unconnected
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.CLK(CLK),
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.CEA(CEA),
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.CEB(CEB),
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.CEC(CEC),
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.CED(CED),
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.CEM(CEM),
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.CECARRYIN(CECARRYIN),
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.CEOPMODE(CEOPMODE),
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.CEP(CEP),
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.RSTA(RSTA),
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.RSTB(RSTB),
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.RSTC(RSTC),
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.RSTD(RSTD),
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.RSTM(RSTM),
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.RSTCARRYIN(RSTCARRYIN),
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.RSTOPMODE(RSTOPMODE),
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.RSTP(RSTP)
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);
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endmodule
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// Spartan 6.
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module DSP48A1 (
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input signed [17:0] A,
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input signed [17:0] B,
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input signed [47:0] C,
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input signed [17:0] D,
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input signed [47:0] PCIN,
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||||
input CARRYIN,
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input [7:0] OPMODE,
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output signed [35:0] M,
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output signed [47:0] P,
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output signed [17:0] BCOUT,
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output signed [47:0] PCOUT,
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output CARRYOUT,
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output CARRYOUTF,
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(* clkbuf_sink *)
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input CLK,
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input CEA,
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input CEB,
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input CEC,
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input CED,
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input CEM,
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input CECARRYIN,
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input CEOPMODE,
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input CEP,
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input RSTA,
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input RSTB,
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input RSTC,
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input RSTD,
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input RSTM,
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input RSTCARRYIN,
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input RSTOPMODE,
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input RSTP
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);
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parameter integer A0REG = 0;
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parameter integer A1REG = 1;
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parameter integer B0REG = 0;
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parameter integer B1REG = 1;
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parameter integer CREG = 1;
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parameter integer DREG = 1;
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parameter integer MREG = 1;
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parameter integer CARRYINREG = 1;
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parameter integer CARRYOUTREG = 1;
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parameter integer OPMODEREG = 1;
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parameter integer PREG = 1;
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parameter CARRYINSEL = "OPMODE5";
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parameter RSTTYPE = "SYNC";
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wire signed [35:0] M_MULT;
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wire signed [47:0] P_IN;
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wire signed [17:0] A0_OUT;
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wire signed [17:0] B0_OUT;
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wire signed [17:0] A1_OUT;
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wire signed [17:0] B1_OUT;
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wire signed [17:0] B1_IN;
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wire signed [47:0] C_OUT;
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wire signed [17:0] D_OUT;
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wire signed [7:0] OPMODE_OUT;
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wire CARRYIN_OUT;
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wire CARRYOUT_IN;
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wire CARRYIN_IN;
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reg signed [47:0] XMUX;
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reg signed [47:0] ZMUX;
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// The registers.
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reg signed [17:0] A0_REG;
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reg signed [17:0] A1_REG;
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reg signed [17:0] B0_REG;
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reg signed [17:0] B1_REG;
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reg signed [47:0] C_REG;
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reg signed [17:0] D_REG;
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reg signed [35:0] M_REG;
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reg signed [47:0] P_REG;
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reg [7:0] OPMODE_REG;
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reg CARRYIN_REG;
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reg CARRYOUT_REG;
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initial begin
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||||
A0_REG = 0;
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A1_REG = 0;
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B0_REG = 0;
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B1_REG = 0;
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C_REG = 0;
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D_REG = 0;
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M_REG = 0;
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P_REG = 0;
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OPMODE_REG = 0;
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CARRYIN_REG = 0;
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CARRYOUT_REG = 0;
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end
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generate
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if (RSTTYPE == "SYNC") begin
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always @(posedge CLK) begin
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if (RSTA) begin
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||||
A0_REG <= 0;
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A1_REG <= 0;
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end else if (CEA) begin
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||||
A0_REG <= A;
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||||
A1_REG <= A0_OUT;
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||||
end
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||||
end
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||||
|
||||
always @(posedge CLK) begin
|
||||
if (RSTB) begin
|
||||
B0_REG <= 0;
|
||||
B1_REG <= 0;
|
||||
end else if (CEB) begin
|
||||
B0_REG <= B;
|
||||
B1_REG <= B1_IN;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if (RSTC) begin
|
||||
C_REG <= 0;
|
||||
end else if (CEC) begin
|
||||
C_REG <= C;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if (RSTD) begin
|
||||
D_REG <= 0;
|
||||
end else if (CED) begin
|
||||
D_REG <= D;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if (RSTM) begin
|
||||
M_REG <= 0;
|
||||
end else if (CEM) begin
|
||||
M_REG <= M_MULT;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if (RSTP) begin
|
||||
P_REG <= 0;
|
||||
end else if (CEP) begin
|
||||
P_REG <= P_IN;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if (RSTOPMODE) begin
|
||||
OPMODE_REG <= 0;
|
||||
end else if (CEOPMODE) begin
|
||||
OPMODE_REG <= OPMODE;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if (RSTCARRYIN) begin
|
||||
CARRYIN_REG <= 0;
|
||||
CARRYOUT_REG <= 0;
|
||||
end else if (CECARRYIN) begin
|
||||
CARRYIN_REG <= CARRYIN_IN;
|
||||
CARRYOUT_REG <= CARRYOUT_IN;
|
||||
end
|
||||
end
|
||||
end else begin
|
||||
always @(posedge CLK, posedge RSTA) begin
|
||||
if (RSTA) begin
|
||||
A0_REG <= 0;
|
||||
A1_REG <= 0;
|
||||
end else if (CEA) begin
|
||||
A0_REG <= A;
|
||||
A1_REG <= A0_OUT;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge CLK, posedge RSTB) begin
|
||||
if (RSTB) begin
|
||||
B0_REG <= 0;
|
||||
B1_REG <= 0;
|
||||
end else if (CEB) begin
|
||||
B0_REG <= B;
|
||||
B1_REG <= B1_IN;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge CLK, posedge RSTC) begin
|
||||
if (RSTC) begin
|
||||
C_REG <= 0;
|
||||
end else if (CEC) begin
|
||||
C_REG <= C;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge CLK, posedge RSTD) begin
|
||||
if (RSTD) begin
|
||||
D_REG <= 0;
|
||||
end else if (CED) begin
|
||||
D_REG <= D;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge CLK, posedge RSTM) begin
|
||||
if (RSTM) begin
|
||||
M_REG <= 0;
|
||||
end else if (CEM) begin
|
||||
M_REG <= M_MULT;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge CLK, posedge RSTP) begin
|
||||
if (RSTP) begin
|
||||
P_REG <= 0;
|
||||
end else if (CEP) begin
|
||||
P_REG <= P_IN;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge CLK, posedge RSTOPMODE) begin
|
||||
if (RSTOPMODE) begin
|
||||
OPMODE_REG <= 0;
|
||||
end else if (CEOPMODE) begin
|
||||
OPMODE_REG <= OPMODE;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge CLK, posedge RSTCARRYIN) begin
|
||||
if (RSTCARRYIN) begin
|
||||
CARRYIN_REG <= 0;
|
||||
CARRYOUT_REG <= 0;
|
||||
end else if (CECARRYIN) begin
|
||||
CARRYIN_REG <= CARRYIN_IN;
|
||||
CARRYOUT_REG <= CARRYOUT_IN;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endgenerate
|
||||
|
||||
// The register enables.
|
||||
assign A0_OUT = (A0REG == 1) ? A0_REG : A;
|
||||
assign A1_OUT = (A1REG == 1) ? A1_REG : A0_OUT;
|
||||
assign B0_OUT = (B0REG == 1) ? B0_REG : B;
|
||||
assign B1_OUT = (B1REG == 1) ? B1_REG : B1_IN;
|
||||
assign C_OUT = (CREG == 1) ? C_REG : C;
|
||||
assign D_OUT = (DREG == 1) ? D_REG : D;
|
||||
assign M = (MREG == 1) ? M_REG : M_MULT;
|
||||
assign P = (PREG == 1) ? P_REG : P_IN;
|
||||
assign OPMODE_OUT = (OPMODEREG == 1) ? OPMODE_REG : OPMODE;
|
||||
assign CARRYIN_OUT = (CARRYINREG == 1) ? CARRYIN_REG : CARRYIN_IN;
|
||||
assign CARRYOUT = (CARRYOUTREG == 1) ? CARRYOUT_REG : CARRYOUT_IN;
|
||||
assign CARRYOUTF = CARRYOUT;
|
||||
|
||||
// The pre-adder.
|
||||
wire signed [17:0] PREADDER;
|
||||
assign B1_IN = OPMODE_OUT[4] ? PREADDER : B0_OUT;
|
||||
assign PREADDER = OPMODE_OUT[6] ? D_OUT - B0_OUT : D_OUT + B0_OUT;
|
||||
|
||||
// The multiplier.
|
||||
assign M_MULT = A1_OUT * B1_OUT;
|
||||
|
||||
// The carry in selection.
|
||||
assign CARRYIN_IN = (CARRYINSEL == "OPMODE5") ? OPMODE_OUT[5] : CARRYIN;
|
||||
|
||||
// The post-adder inputs.
|
||||
always @* begin
|
||||
case (OPMODE_OUT[1:0])
|
||||
2'b00: XMUX <= 0;
|
||||
2'b01: XMUX <= M;
|
||||
2'b10: XMUX <= P;
|
||||
2'b11: XMUX <= {D_OUT[11:0], B1_OUT, A1_OUT};
|
||||
default: XMUX <= 48'hxxxxxxxxxxxx;
|
||||
endcase
|
||||
end
|
||||
|
||||
always @* begin
|
||||
case (OPMODE_OUT[3:2])
|
||||
2'b00: ZMUX <= 0;
|
||||
2'b01: ZMUX <= PCIN;
|
||||
2'b10: ZMUX <= P;
|
||||
2'b11: ZMUX <= C_OUT;
|
||||
default: ZMUX <= 48'hxxxxxxxxxxxx;
|
||||
endcase
|
||||
end
|
||||
|
||||
// The post-adder.
|
||||
wire signed [48:0] X_EXT;
|
||||
wire signed [48:0] Z_EXT;
|
||||
assign X_EXT = XMUX;
|
||||
assign Z_EXT = ZMUX;
|
||||
assign {CARRYOUT_IN, P_IN} = OPMODE_OUT[7] ? (Z_EXT - (X_EXT + CARRYIN_OUT)) : (Z_EXT + X_EXT + CARRYIN_OUT);
|
||||
|
||||
// Cascade outputs.
|
||||
assign BCOUT = B1_OUT;
|
||||
assign PCOUT = P;
|
||||
|
||||
endmodule
|
||||
|
||||
// TODO: DSP48 (Virtex 4).
|
||||
|
||||
// TODO: DSP48E (Virtex 5).
|
||||
|
||||
// Virtex 6, Series 7.
|
||||
|
||||
module DSP48E1 (
|
||||
output [29:0] ACOUT,
|
||||
output [17:0] BCOUT,
|
||||
|
|
@ -1040,3 +1560,5 @@ module DSP48E1 (
|
|||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
// TODO: DSP48E2 (Ultrascale).
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue