mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-31 03:32:29 +00:00
Merge remote-tracking branch 'origin/master' into xaig_dff
This commit is contained in:
Eddie Hung
commit
09ee96e8c2
228 changed files with 35110 additions and 24029 deletions
|
|
@ -13,7 +13,7 @@ EXTRA_OBJS += techlibs/xilinx/brams_init.mk
|
|||
|
||||
techlibs/xilinx/brams_init.mk: techlibs/xilinx/brams_init.py
|
||||
$(Q) mkdir -p techlibs/xilinx
|
||||
$(P) python3 $<
|
||||
$(P) $(PYTHON_EXECUTABLE) $<
|
||||
$(Q) touch $@
|
||||
|
||||
techlibs/xilinx/brams_init_36.vh: techlibs/xilinx/brams_init.mk
|
||||
|
|
@ -25,16 +25,14 @@ techlibs/xilinx/brams_init_8.vh: techlibs/xilinx/brams_init.mk
|
|||
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_map.v))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_sim.v))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_cells_xtra.v))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6v_cells_xtra.v))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_cells_xtra.v))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcu_cells_xtra.v))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_xtra.v))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams.txt))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams_map.v))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams_bb.v))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams.txt))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_xcu_brams.txt))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams_map.v))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams_bb.v))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcu_brams_map.v))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcup_urams.txt))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcup_urams_map.v))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams.txt))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams_map.v))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v))
|
||||
|
|
@ -42,7 +40,13 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_ff_map.v))
|
|||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_ff_map.v))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/mux_map.v))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/dsp_map.v))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc3s_mult_map.v))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc3sda_dsp_map.v))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_dsp_map.v))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc4v_dsp_map.v))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc5v_dsp_map.v))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_dsp_map.v))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcu_dsp_map.v))
|
||||
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_map.v))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_unmap.v))
|
||||
|
|
|
|||
|
|
@ -38,6 +38,17 @@ module IBUF(
|
|||
assign O = I;
|
||||
endmodule
|
||||
|
||||
module IBUFG(
|
||||
output O,
|
||||
(* iopad_external_pin *)
|
||||
input I);
|
||||
parameter CAPACITANCE = "DONT_CARE";
|
||||
parameter IBUF_DELAY_VALUE = "0";
|
||||
parameter IBUF_LOW_PWR = "TRUE";
|
||||
parameter IOSTANDARD = "DEFAULT";
|
||||
assign O = I;
|
||||
endmodule
|
||||
|
||||
module OBUF(
|
||||
(* iopad_external_pin *)
|
||||
output O,
|
||||
|
|
@ -578,6 +589,515 @@ module SRLC32E (
|
|||
endgenerate
|
||||
endmodule
|
||||
|
||||
// DSP
|
||||
|
||||
// Virtex 2, Virtex 2 Pro, Spartan 3.
|
||||
|
||||
// Asynchronous mode.
|
||||
|
||||
module MULT18X18 (
|
||||
input signed [17:0] A,
|
||||
input signed [17:0] B,
|
||||
output signed [35:0] P
|
||||
);
|
||||
|
||||
assign P = A * B;
|
||||
|
||||
endmodule
|
||||
|
||||
// Synchronous mode.
|
||||
|
||||
module MULT18X18S (
|
||||
input signed [17:0] A,
|
||||
input signed [17:0] B,
|
||||
output reg signed [35:0] P,
|
||||
(* clkbuf_sink *)
|
||||
input C,
|
||||
input CE,
|
||||
input R
|
||||
);
|
||||
|
||||
always @(posedge C)
|
||||
if (R)
|
||||
P <= 0;
|
||||
else if (CE)
|
||||
P <= A * B;
|
||||
|
||||
endmodule
|
||||
|
||||
// Spartan 3E, Spartan 3A.
|
||||
|
||||
module MULT18X18SIO (
|
||||
input signed [17:0] A,
|
||||
input signed [17:0] B,
|
||||
output signed [35:0] P,
|
||||
(* clkbuf_sink *)
|
||||
input CLK,
|
||||
input CEA,
|
||||
input CEB,
|
||||
input CEP,
|
||||
input RSTA,
|
||||
input RSTB,
|
||||
input RSTP,
|
||||
input signed [17:0] BCIN,
|
||||
output signed [17:0] BCOUT
|
||||
);
|
||||
|
||||
parameter integer AREG = 1;
|
||||
parameter integer BREG = 1;
|
||||
parameter B_INPUT = "DIRECT";
|
||||
parameter integer PREG = 1;
|
||||
|
||||
// The multiplier.
|
||||
wire signed [35:0] P_MULT;
|
||||
assign P_MULT = A_MULT * B_MULT;
|
||||
|
||||
// The cascade output.
|
||||
assign BCOUT = B_MULT;
|
||||
|
||||
// The B input multiplexer.
|
||||
wire signed [17:0] B_MUX;
|
||||
assign B_MUX = (B_INPUT == "DIRECT") ? B : BCIN;
|
||||
|
||||
// The registers.
|
||||
reg signed [17:0] A_REG;
|
||||
reg signed [17:0] B_REG;
|
||||
reg signed [35:0] P_REG;
|
||||
|
||||
initial begin
|
||||
A_REG = 0;
|
||||
B_REG = 0;
|
||||
P_REG = 0;
|
||||
end
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if (RSTA)
|
||||
A_REG <= 0;
|
||||
else if (CEA)
|
||||
A_REG <= A;
|
||||
|
||||
if (RSTB)
|
||||
B_REG <= 0;
|
||||
else if (CEB)
|
||||
B_REG <= B_MUX;
|
||||
|
||||
if (RSTP)
|
||||
P_REG <= 0;
|
||||
else if (CEP)
|
||||
P_REG <= P_MULT;
|
||||
end
|
||||
|
||||
// The register enables.
|
||||
wire signed [17:0] A_MULT;
|
||||
wire signed [17:0] B_MULT;
|
||||
assign A_MULT = (AREG == 1) ? A_REG : A;
|
||||
assign B_MULT = (BREG == 1) ? B_REG : B_MUX;
|
||||
assign P = (PREG == 1) ? P_REG : P_MULT;
|
||||
|
||||
endmodule
|
||||
|
||||
// Spartan 3A DSP.
|
||||
|
||||
module DSP48A (
|
||||
input signed [17:0] A,
|
||||
input signed [17:0] B,
|
||||
input signed [47:0] C,
|
||||
input signed [17:0] D,
|
||||
input signed [47:0] PCIN,
|
||||
input CARRYIN,
|
||||
input [7:0] OPMODE,
|
||||
output signed [47:0] P,
|
||||
output signed [17:0] BCOUT,
|
||||
output signed [47:0] PCOUT,
|
||||
output CARRYOUT,
|
||||
(* clkbuf_sink *)
|
||||
input CLK,
|
||||
input CEA,
|
||||
input CEB,
|
||||
input CEC,
|
||||
input CED,
|
||||
input CEM,
|
||||
input CECARRYIN,
|
||||
input CEOPMODE,
|
||||
input CEP,
|
||||
input RSTA,
|
||||
input RSTB,
|
||||
input RSTC,
|
||||
input RSTD,
|
||||
input RSTM,
|
||||
input RSTCARRYIN,
|
||||
input RSTOPMODE,
|
||||
input RSTP
|
||||
);
|
||||
|
||||
parameter integer A0REG = 0;
|
||||
parameter integer A1REG = 1;
|
||||
parameter integer B0REG = 0;
|
||||
parameter integer B1REG = 1;
|
||||
parameter integer CREG = 1;
|
||||
parameter integer DREG = 1;
|
||||
parameter integer MREG = 1;
|
||||
parameter integer CARRYINREG = 1;
|
||||
parameter integer OPMODEREG = 1;
|
||||
parameter integer PREG = 1;
|
||||
parameter CARRYINSEL = "CARRYIN";
|
||||
parameter RSTTYPE = "SYNC";
|
||||
|
||||
// This is a strict subset of Spartan 6 -- reuse its model.
|
||||
|
||||
DSP48A1 #(
|
||||
.A0REG(A0REG),
|
||||
.A1REG(A1REG),
|
||||
.B0REG(B0REG),
|
||||
.B1REG(B1REG),
|
||||
.CREG(CREG),
|
||||
.DREG(DREG),
|
||||
.MREG(MREG),
|
||||
.CARRYINREG(CARRYINREG),
|
||||
.CARRYOUTREG(0),
|
||||
.OPMODEREG(OPMODEREG),
|
||||
.PREG(PREG),
|
||||
.CARRYINSEL(CARRYINSEL),
|
||||
.RSTTYPE(RSTTYPE)
|
||||
) upgrade (
|
||||
.A(A),
|
||||
.B(B),
|
||||
.C(C),
|
||||
.D(D),
|
||||
.PCIN(PCIN),
|
||||
.CARRYIN(CARRYIN),
|
||||
.OPMODE(OPMODE),
|
||||
// M unconnected
|
||||
.P(P),
|
||||
.BCOUT(BCOUT),
|
||||
.PCOUT(PCOUT),
|
||||
.CARRYOUT(CARRYOUT),
|
||||
// CARRYOUTF unconnected
|
||||
.CLK(CLK),
|
||||
.CEA(CEA),
|
||||
.CEB(CEB),
|
||||
.CEC(CEC),
|
||||
.CED(CED),
|
||||
.CEM(CEM),
|
||||
.CECARRYIN(CECARRYIN),
|
||||
.CEOPMODE(CEOPMODE),
|
||||
.CEP(CEP),
|
||||
.RSTA(RSTA),
|
||||
.RSTB(RSTB),
|
||||
.RSTC(RSTC),
|
||||
.RSTD(RSTD),
|
||||
.RSTM(RSTM),
|
||||
.RSTCARRYIN(RSTCARRYIN),
|
||||
.RSTOPMODE(RSTOPMODE),
|
||||
.RSTP(RSTP)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
// Spartan 6.
|
||||
|
||||
module DSP48A1 (
|
||||
input signed [17:0] A,
|
||||
input signed [17:0] B,
|
||||
input signed [47:0] C,
|
||||
input signed [17:0] D,
|
||||
input signed [47:0] PCIN,
|
||||
input CARRYIN,
|
||||
input [7:0] OPMODE,
|
||||
output signed [35:0] M,
|
||||
output signed [47:0] P,
|
||||
output signed [17:0] BCOUT,
|
||||
output signed [47:0] PCOUT,
|
||||
output CARRYOUT,
|
||||
output CARRYOUTF,
|
||||
(* clkbuf_sink *)
|
||||
input CLK,
|
||||
input CEA,
|
||||
input CEB,
|
||||
input CEC,
|
||||
input CED,
|
||||
input CEM,
|
||||
input CECARRYIN,
|
||||
input CEOPMODE,
|
||||
input CEP,
|
||||
input RSTA,
|
||||
input RSTB,
|
||||
input RSTC,
|
||||
input RSTD,
|
||||
input RSTM,
|
||||
input RSTCARRYIN,
|
||||
input RSTOPMODE,
|
||||
input RSTP
|
||||
);
|
||||
|
||||
parameter integer A0REG = 0;
|
||||
parameter integer A1REG = 1;
|
||||
parameter integer B0REG = 0;
|
||||
parameter integer B1REG = 1;
|
||||
parameter integer CREG = 1;
|
||||
parameter integer DREG = 1;
|
||||
parameter integer MREG = 1;
|
||||
parameter integer CARRYINREG = 1;
|
||||
parameter integer CARRYOUTREG = 1;
|
||||
parameter integer OPMODEREG = 1;
|
||||
parameter integer PREG = 1;
|
||||
parameter CARRYINSEL = "OPMODE5";
|
||||
parameter RSTTYPE = "SYNC";
|
||||
|
||||
wire signed [35:0] M_MULT;
|
||||
wire signed [47:0] P_IN;
|
||||
wire signed [17:0] A0_OUT;
|
||||
wire signed [17:0] B0_OUT;
|
||||
wire signed [17:0] A1_OUT;
|
||||
wire signed [17:0] B1_OUT;
|
||||
wire signed [17:0] B1_IN;
|
||||
wire signed [47:0] C_OUT;
|
||||
wire signed [17:0] D_OUT;
|
||||
wire signed [7:0] OPMODE_OUT;
|
||||
wire CARRYIN_OUT;
|
||||
wire CARRYOUT_IN;
|
||||
wire CARRYIN_IN;
|
||||
reg signed [47:0] XMUX;
|
||||
reg signed [47:0] ZMUX;
|
||||
|
||||
// The registers.
|
||||
reg signed [17:0] A0_REG;
|
||||
reg signed [17:0] A1_REG;
|
||||
reg signed [17:0] B0_REG;
|
||||
reg signed [17:0] B1_REG;
|
||||
reg signed [47:0] C_REG;
|
||||
reg signed [17:0] D_REG;
|
||||
reg signed [35:0] M_REG;
|
||||
reg signed [47:0] P_REG;
|
||||
reg [7:0] OPMODE_REG;
|
||||
reg CARRYIN_REG;
|
||||
reg CARRYOUT_REG;
|
||||
|
||||
initial begin
|
||||
A0_REG = 0;
|
||||
A1_REG = 0;
|
||||
B0_REG = 0;
|
||||
B1_REG = 0;
|
||||
C_REG = 0;
|
||||
D_REG = 0;
|
||||
M_REG = 0;
|
||||
P_REG = 0;
|
||||
OPMODE_REG = 0;
|
||||
CARRYIN_REG = 0;
|
||||
CARRYOUT_REG = 0;
|
||||
end
|
||||
|
||||
generate
|
||||
|
||||
if (RSTTYPE == "SYNC") begin
|
||||
always @(posedge CLK) begin
|
||||
if (RSTA) begin
|
||||
A0_REG <= 0;
|
||||
A1_REG <= 0;
|
||||
end else if (CEA) begin
|
||||
A0_REG <= A;
|
||||
A1_REG <= A0_OUT;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if (RSTB) begin
|
||||
B0_REG <= 0;
|
||||
B1_REG <= 0;
|
||||
end else if (CEB) begin
|
||||
B0_REG <= B;
|
||||
B1_REG <= B1_IN;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if (RSTC) begin
|
||||
C_REG <= 0;
|
||||
end else if (CEC) begin
|
||||
C_REG <= C;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if (RSTD) begin
|
||||
D_REG <= 0;
|
||||
end else if (CED) begin
|
||||
D_REG <= D;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if (RSTM) begin
|
||||
M_REG <= 0;
|
||||
end else if (CEM) begin
|
||||
M_REG <= M_MULT;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if (RSTP) begin
|
||||
P_REG <= 0;
|
||||
end else if (CEP) begin
|
||||
P_REG <= P_IN;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if (RSTOPMODE) begin
|
||||
OPMODE_REG <= 0;
|
||||
end else if (CEOPMODE) begin
|
||||
OPMODE_REG <= OPMODE;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if (RSTCARRYIN) begin
|
||||
CARRYIN_REG <= 0;
|
||||
CARRYOUT_REG <= 0;
|
||||
end else if (CECARRYIN) begin
|
||||
CARRYIN_REG <= CARRYIN_IN;
|
||||
CARRYOUT_REG <= CARRYOUT_IN;
|
||||
end
|
||||
end
|
||||
end else begin
|
||||
always @(posedge CLK, posedge RSTA) begin
|
||||
if (RSTA) begin
|
||||
A0_REG <= 0;
|
||||
A1_REG <= 0;
|
||||
end else if (CEA) begin
|
||||
A0_REG <= A;
|
||||
A1_REG <= A0_OUT;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge CLK, posedge RSTB) begin
|
||||
if (RSTB) begin
|
||||
B0_REG <= 0;
|
||||
B1_REG <= 0;
|
||||
end else if (CEB) begin
|
||||
B0_REG <= B;
|
||||
B1_REG <= B1_IN;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge CLK, posedge RSTC) begin
|
||||
if (RSTC) begin
|
||||
C_REG <= 0;
|
||||
end else if (CEC) begin
|
||||
C_REG <= C;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge CLK, posedge RSTD) begin
|
||||
if (RSTD) begin
|
||||
D_REG <= 0;
|
||||
end else if (CED) begin
|
||||
D_REG <= D;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge CLK, posedge RSTM) begin
|
||||
if (RSTM) begin
|
||||
M_REG <= 0;
|
||||
end else if (CEM) begin
|
||||
M_REG <= M_MULT;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge CLK, posedge RSTP) begin
|
||||
if (RSTP) begin
|
||||
P_REG <= 0;
|
||||
end else if (CEP) begin
|
||||
P_REG <= P_IN;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge CLK, posedge RSTOPMODE) begin
|
||||
if (RSTOPMODE) begin
|
||||
OPMODE_REG <= 0;
|
||||
end else if (CEOPMODE) begin
|
||||
OPMODE_REG <= OPMODE;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge CLK, posedge RSTCARRYIN) begin
|
||||
if (RSTCARRYIN) begin
|
||||
CARRYIN_REG <= 0;
|
||||
CARRYOUT_REG <= 0;
|
||||
end else if (CECARRYIN) begin
|
||||
CARRYIN_REG <= CARRYIN_IN;
|
||||
CARRYOUT_REG <= CARRYOUT_IN;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endgenerate
|
||||
|
||||
// The register enables.
|
||||
assign A0_OUT = (A0REG == 1) ? A0_REG : A;
|
||||
assign A1_OUT = (A1REG == 1) ? A1_REG : A0_OUT;
|
||||
assign B0_OUT = (B0REG == 1) ? B0_REG : B;
|
||||
assign B1_OUT = (B1REG == 1) ? B1_REG : B1_IN;
|
||||
assign C_OUT = (CREG == 1) ? C_REG : C;
|
||||
assign D_OUT = (DREG == 1) ? D_REG : D;
|
||||
assign M = (MREG == 1) ? M_REG : M_MULT;
|
||||
assign P = (PREG == 1) ? P_REG : P_IN;
|
||||
assign OPMODE_OUT = (OPMODEREG == 1) ? OPMODE_REG : OPMODE;
|
||||
assign CARRYIN_OUT = (CARRYINREG == 1) ? CARRYIN_REG : CARRYIN_IN;
|
||||
assign CARRYOUT = (CARRYOUTREG == 1) ? CARRYOUT_REG : CARRYOUT_IN;
|
||||
assign CARRYOUTF = CARRYOUT;
|
||||
|
||||
// The pre-adder.
|
||||
wire signed [17:0] PREADDER;
|
||||
assign B1_IN = OPMODE_OUT[4] ? PREADDER : B0_OUT;
|
||||
assign PREADDER = OPMODE_OUT[6] ? D_OUT - B0_OUT : D_OUT + B0_OUT;
|
||||
|
||||
// The multiplier.
|
||||
assign M_MULT = A1_OUT * B1_OUT;
|
||||
|
||||
// The carry in selection.
|
||||
assign CARRYIN_IN = (CARRYINSEL == "OPMODE5") ? OPMODE_OUT[5] : CARRYIN;
|
||||
|
||||
// The post-adder inputs.
|
||||
always @* begin
|
||||
case (OPMODE_OUT[1:0])
|
||||
2'b00: XMUX <= 0;
|
||||
2'b01: XMUX <= M;
|
||||
2'b10: XMUX <= P;
|
||||
2'b11: XMUX <= {D_OUT[11:0], B1_OUT, A1_OUT};
|
||||
default: XMUX <= 48'hxxxxxxxxxxxx;
|
||||
endcase
|
||||
end
|
||||
|
||||
always @* begin
|
||||
case (OPMODE_OUT[3:2])
|
||||
2'b00: ZMUX <= 0;
|
||||
2'b01: ZMUX <= PCIN;
|
||||
2'b10: ZMUX <= P;
|
||||
2'b11: ZMUX <= C_OUT;
|
||||
default: ZMUX <= 48'hxxxxxxxxxxxx;
|
||||
endcase
|
||||
end
|
||||
|
||||
// The post-adder.
|
||||
wire signed [48:0] X_EXT;
|
||||
wire signed [48:0] Z_EXT;
|
||||
assign X_EXT = XMUX;
|
||||
assign Z_EXT = ZMUX;
|
||||
assign {CARRYOUT_IN, P_IN} = OPMODE_OUT[7] ? (Z_EXT - (X_EXT + CARRYIN_OUT)) : (Z_EXT + X_EXT + CARRYIN_OUT);
|
||||
|
||||
// Cascade outputs.
|
||||
assign BCOUT = B1_OUT;
|
||||
assign PCOUT = P;
|
||||
|
||||
endmodule
|
||||
|
||||
// TODO: DSP48 (Virtex 4).
|
||||
|
||||
// TODO: DSP48E (Virtex 5).
|
||||
|
||||
// Virtex 6, Series 7.
|
||||
|
||||
module DSP48E1 (
|
||||
output [29:0] ACOUT,
|
||||
output [17:0] BCOUT,
|
||||
|
|
@ -1040,3 +1560,5 @@ module DSP48E1 (
|
|||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
// TODO: DSP48E2 (Ultrascale).
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
29212
techlibs/xilinx/cells_xtra.v
Normal file
29212
techlibs/xilinx/cells_xtra.v
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -46,7 +46,7 @@ struct SynthXilinxPass : public ScriptPass
|
|||
log(" -top <module>\n");
|
||||
log(" use the specified module as top module\n");
|
||||
log("\n");
|
||||
log(" -family {xcup|xcu|xc7|xc6v|xc6s}\n");
|
||||
log(" -family {xcup|xcu|xc7|xc6v|xc5v|xc6s}\n");
|
||||
log(" run synthesis for the specified Xilinx architecture\n");
|
||||
log(" generate the synthesis netlist for the specified family.\n");
|
||||
log(" default: xc7\n");
|
||||
|
|
@ -93,6 +93,9 @@ struct SynthXilinxPass : public ScriptPass
|
|||
log(" -noclkbuf\n");
|
||||
log(" disable automatic clock buffer insertion\n");
|
||||
log("\n");
|
||||
log(" -uram\n");
|
||||
log(" infer URAM288s for large memories (xcup only)\n");
|
||||
log("\n");
|
||||
log(" -widemux <int>\n");
|
||||
log(" enable inference of hard multiplexer resources (MUXF[78]) for muxes at or\n");
|
||||
log(" above this number of inputs (minimum value 2, recommended value >= 5).\n");
|
||||
|
|
@ -119,7 +122,7 @@ struct SynthXilinxPass : public ScriptPass
|
|||
}
|
||||
|
||||
std::string top_opt, edif_file, blif_file, family;
|
||||
bool flatten, retime, vpr, ise, iopad, noiopad, noclkbuf, nobram, nolutram, nosrl, nocarry, nowidelut, nodsp, abc9;
|
||||
bool flatten, retime, vpr, ise, iopad, noiopad, noclkbuf, nobram, nolutram, nosrl, nocarry, nowidelut, nodsp, uram, abc9;
|
||||
bool flatten_before_abc;
|
||||
int widemux;
|
||||
|
||||
|
|
@ -143,6 +146,7 @@ struct SynthXilinxPass : public ScriptPass
|
|||
nocarry = false;
|
||||
nowidelut = false;
|
||||
nodsp = false;
|
||||
uram = false;
|
||||
abc9 = false;
|
||||
flatten_before_abc = false;
|
||||
widemux = 0;
|
||||
|
|
@ -248,11 +252,15 @@ struct SynthXilinxPass : public ScriptPass
|
|||
nodsp = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-uram") {
|
||||
uram = true;
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
}
|
||||
extra_args(args, argidx, design);
|
||||
|
||||
if (family != "xcup" && family != "xcu" && family != "xc7" && family != "xc6v" && family != "xc6s")
|
||||
if (family != "xcup" && family != "xcu" && family != "xc7" && family != "xc6v" && family != "xc5v" && family != "xc6s")
|
||||
log_cmd_error("Invalid Xilinx -family setting: '%s'.\n", family.c_str());
|
||||
|
||||
if (widemux != 0 && widemux < 2)
|
||||
|
|
@ -289,24 +297,7 @@ struct SynthXilinxPass : public ScriptPass
|
|||
read_args += " -lib +/xilinx/cells_sim.v";
|
||||
run("read_verilog" + read_args);
|
||||
|
||||
if (help_mode)
|
||||
run("read_verilog -lib +/xilinx/{family}_cells_xtra.v");
|
||||
else if (family == "xc6s")
|
||||
run("read_verilog -lib +/xilinx/xc6s_cells_xtra.v");
|
||||
else if (family == "xc6v")
|
||||
run("read_verilog -lib +/xilinx/xc6v_cells_xtra.v");
|
||||
else if (family == "xc7")
|
||||
run("read_verilog -lib +/xilinx/xc7_cells_xtra.v");
|
||||
else if (family == "xcu" || family == "xcup")
|
||||
run("read_verilog -lib +/xilinx/xcu_cells_xtra.v");
|
||||
|
||||
if (help_mode) {
|
||||
run("read_verilog -lib +/xilinx/{family}_brams_bb.v");
|
||||
} else if (family == "xc6s") {
|
||||
run("read_verilog -lib +/xilinx/xc6s_brams_bb.v");
|
||||
} else if (family == "xc6v" || family == "xc7") {
|
||||
run("read_verilog -lib +/xilinx/xc7_brams_bb.v");
|
||||
}
|
||||
run("read_verilog -lib +/xilinx/cells_xtra.v");
|
||||
|
||||
run(stringf("hierarchy -check %s", top_opt.c_str()));
|
||||
}
|
||||
|
|
@ -342,15 +333,53 @@ struct SynthXilinxPass : public ScriptPass
|
|||
|
||||
if (check_label("map_dsp", "(skip if '-nodsp')")) {
|
||||
if (!nodsp || help_mode) {
|
||||
run("memory_dff"); // xilinx_dsp will merge registers, reserve memory port registers first
|
||||
// NB: Xilinx multipliers are signed only
|
||||
run("techmap -map +/mul2dsp.v -map +/xilinx/dsp_map.v -D DSP_A_MAXWIDTH=25 "
|
||||
"-D DSP_A_MAXWIDTH_PARTIAL=18 -D DSP_B_MAXWIDTH=18 " // Partial multipliers are intentionally
|
||||
// limited to 18x18 in order to take
|
||||
// advantage of the (PCOUT << 17) -> PCIN
|
||||
// dedicated cascade chain capability
|
||||
"-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers
|
||||
"-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller
|
||||
"-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18");
|
||||
if (help_mode)
|
||||
run("techmap -map +/mul2dsp.v -map +/xilinx/{family}_dsp_map.v {options}");
|
||||
else if (family == "xc2v" || family == "xc3s" || family == "xc3se" || family == "xc3sa")
|
||||
run("techmap -map +/mul2dsp.v -map +/xilinx/xc3s_mult_map.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 "
|
||||
"-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers
|
||||
"-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller
|
||||
"-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL18X18");
|
||||
else if (family == "xc3sda")
|
||||
run("techmap -map +/mul2dsp.v -map +/xilinx/xc3sda_dsp_map.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 "
|
||||
"-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers
|
||||
"-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller
|
||||
"-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL18X18");
|
||||
else if (family == "xc6s")
|
||||
run("techmap -map +/mul2dsp.v -map +/xilinx/xc6s_dsp_map.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 "
|
||||
"-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers
|
||||
"-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller
|
||||
"-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL18X18");
|
||||
else if (family == "xc4v")
|
||||
run("techmap -map +/mul2dsp.v -map +/xilinx/xc4v_dsp_map.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 "
|
||||
"-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers
|
||||
"-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller
|
||||
"-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL18X18");
|
||||
else if (family == "xc5v")
|
||||
run("techmap -map +/mul2dsp.v -map +/xilinx/xc5v_dsp_map.v -D DSP_A_MAXWIDTH=25 -D DSP_B_MAXWIDTH=18 "
|
||||
"-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers
|
||||
"-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller
|
||||
"-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18");
|
||||
else if (family == "xc6v" || family == "xc7")
|
||||
run("techmap -map +/mul2dsp.v -map +/xilinx/xc7_dsp_map.v -D DSP_A_MAXWIDTH=25 -D DSP_B_MAXWIDTH=18 "
|
||||
"-D DSP_A_MAXWIDTH_PARTIAL=18 " // Partial multipliers are intentionally
|
||||
// limited to 18x18 in order to take
|
||||
// advantage of the (PCOUT << 17) -> PCIN
|
||||
// dedicated cascade chain capability
|
||||
"-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers
|
||||
"-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller
|
||||
"-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18");
|
||||
else if (family == "xcu" || family == "xcup")
|
||||
run("techmap -map +/mul2dsp.v -map +/xilinx/xcu_dsp_map.v -D DSP_A_MAXWIDTH=27 -D DSP_B_MAXWIDTH=18 "
|
||||
"-D DSP_A_MAXWIDTH_PARTIAL=18 " // Partial multipliers are intentionally
|
||||
// limited to 18x18 in order to take
|
||||
// advantage of the (PCOUT << 17) -> PCIN
|
||||
// dedicated cascade chain capability
|
||||
"-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers
|
||||
"-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller
|
||||
"-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL27X18");
|
||||
run("select a:mul2dsp");
|
||||
run("setattr -unset mul2dsp");
|
||||
run("opt_expr -fine");
|
||||
|
|
@ -371,6 +400,20 @@ struct SynthXilinxPass : public ScriptPass
|
|||
run("opt_clean");
|
||||
}
|
||||
|
||||
if (check_label("map_uram", "(only if '-uram')")) {
|
||||
if (help_mode) {
|
||||
run("memory_bram -rules +/xilinx/{family}_urams.txt");
|
||||
run("techmap -map +/xilinx/{family}_urams_map.v");
|
||||
} else if (uram) {
|
||||
if (family == "xcup") {
|
||||
run("memory_bram -rules +/xilinx/xcup_urams.txt");
|
||||
run("techmap -map +/xilinx/xcup_urams_map.v");
|
||||
} else {
|
||||
log_warning("UltraRAM inference not supported for family %s.\n", family.c_str());
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (check_label("map_bram", "(skip if '-nobram')")) {
|
||||
if (help_mode) {
|
||||
run("memory_bram -rules +/xilinx/{family}_brams.txt");
|
||||
|
|
@ -380,8 +423,11 @@ struct SynthXilinxPass : public ScriptPass
|
|||
run("memory_bram -rules +/xilinx/xc6s_brams.txt");
|
||||
run("techmap -map +/xilinx/xc6s_brams_map.v");
|
||||
} else if (family == "xc6v" || family == "xc7") {
|
||||
run("memory_bram -rules +/xilinx/xc7_brams.txt");
|
||||
run("memory_bram -rules +/xilinx/xc7_xcu_brams.txt");
|
||||
run("techmap -map +/xilinx/xc7_brams_map.v");
|
||||
} else if (family == "xcu" || family == "xcup") {
|
||||
run("memory_bram -rules +/xilinx/xc7_xcu_brams.txt");
|
||||
run("techmap -map +/xilinx/xcu_brams_map.v");
|
||||
} else {
|
||||
log_warning("Block RAM inference not yet supported for family %s.\n", family.c_str());
|
||||
}
|
||||
|
|
|
|||
14
techlibs/xilinx/xc3s_mult_map.v
Normal file
14
techlibs/xilinx/xc3s_mult_map.v
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y);
|
||||
parameter A_SIGNED = 0;
|
||||
parameter B_SIGNED = 0;
|
||||
parameter A_WIDTH = 0;
|
||||
parameter B_WIDTH = 0;
|
||||
parameter Y_WIDTH = 0;
|
||||
|
||||
MULT18X18 _TECHMAP_REPLACE_ (
|
||||
.A(A),
|
||||
.B(B),
|
||||
.P(Y)
|
||||
);
|
||||
endmodule
|
||||
|
||||
34
techlibs/xilinx/xc3sda_dsp_map.v
Normal file
34
techlibs/xilinx/xc3sda_dsp_map.v
Normal file
|
|
@ -0,0 +1,34 @@
|
|||
module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y);
|
||||
parameter A_SIGNED = 0;
|
||||
parameter B_SIGNED = 0;
|
||||
parameter A_WIDTH = 0;
|
||||
parameter B_WIDTH = 0;
|
||||
parameter Y_WIDTH = 0;
|
||||
|
||||
wire [47:0] P_48;
|
||||
DSP48A #(
|
||||
// Disable all registers
|
||||
.A0REG(0),
|
||||
.A1REG(0),
|
||||
.B0REG(0),
|
||||
.B1REG(0),
|
||||
.CARRYINREG(0),
|
||||
.CARRYINSEL("OPMODE5"),
|
||||
.CREG(0),
|
||||
.DREG(0),
|
||||
.MREG(0),
|
||||
.OPMODEREG(0),
|
||||
.PREG(0)
|
||||
) _TECHMAP_REPLACE_ (
|
||||
//Data path
|
||||
.A(A),
|
||||
.B(B),
|
||||
.C(48'b0),
|
||||
.D(18'b0),
|
||||
.P(P_48),
|
||||
|
||||
.OPMODE(8'b0000010)
|
||||
);
|
||||
assign Y = P_48;
|
||||
endmodule
|
||||
|
||||
38
techlibs/xilinx/xc4v_dsp_map.v
Normal file
38
techlibs/xilinx/xc4v_dsp_map.v
Normal file
|
|
@ -0,0 +1,38 @@
|
|||
module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y);
|
||||
parameter A_SIGNED = 0;
|
||||
parameter B_SIGNED = 0;
|
||||
parameter A_WIDTH = 0;
|
||||
parameter B_WIDTH = 0;
|
||||
parameter Y_WIDTH = 0;
|
||||
|
||||
wire [47:0] P_48;
|
||||
DSP48 #(
|
||||
// Disable all registers
|
||||
.AREG(0),
|
||||
.BREG(0),
|
||||
.B_INPUT("DIRECT"),
|
||||
.CARRYINREG(0),
|
||||
.CARRYINSELREG(0),
|
||||
.CREG(0),
|
||||
.MREG(0),
|
||||
.OPMODEREG(0),
|
||||
.PREG(0),
|
||||
.SUBTRACTREG(0),
|
||||
.LEGACY_MODE("MULT18X18")
|
||||
) _TECHMAP_REPLACE_ (
|
||||
//Data path
|
||||
.A(A),
|
||||
.B(B),
|
||||
.C(48'b0),
|
||||
.P(P_48),
|
||||
|
||||
.SUBTRACT(1'b0),
|
||||
.OPMODE(7'b000101),
|
||||
.CARRYINSEL(2'b00),
|
||||
|
||||
.BCIN(18'b0),
|
||||
.PCIN(48'b0),
|
||||
.CARRYIN(1'b0)
|
||||
);
|
||||
assign Y = P_48;
|
||||
endmodule
|
||||
45
techlibs/xilinx/xc5v_dsp_map.v
Normal file
45
techlibs/xilinx/xc5v_dsp_map.v
Normal file
|
|
@ -0,0 +1,45 @@
|
|||
module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] Y);
|
||||
parameter A_SIGNED = 0;
|
||||
parameter B_SIGNED = 0;
|
||||
parameter A_WIDTH = 0;
|
||||
parameter B_WIDTH = 0;
|
||||
parameter Y_WIDTH = 0;
|
||||
|
||||
wire [47:0] P_48;
|
||||
DSP48E #(
|
||||
// Disable all registers
|
||||
.ACASCREG(0),
|
||||
.A_INPUT("DIRECT"),
|
||||
.ALUMODEREG(0),
|
||||
.AREG(0),
|
||||
.BCASCREG(0),
|
||||
.B_INPUT("DIRECT"),
|
||||
.BREG(0),
|
||||
.MULTCARRYINREG(0),
|
||||
.CARRYINREG(0),
|
||||
.CARRYINSELREG(0),
|
||||
.CREG(0),
|
||||
.MREG(0),
|
||||
.OPMODEREG(0),
|
||||
.PREG(0),
|
||||
.USE_MULT("MULT"),
|
||||
.USE_SIMD("ONE48")
|
||||
) _TECHMAP_REPLACE_ (
|
||||
//Data path
|
||||
.A({{5{A[24]}}, A}),
|
||||
.B(B),
|
||||
.C(48'b0),
|
||||
.P(P_48),
|
||||
|
||||
.ALUMODE(4'b0000),
|
||||
.OPMODE(7'b000101),
|
||||
.CARRYINSEL(3'b000),
|
||||
|
||||
.ACIN(30'b0),
|
||||
.BCIN(18'b0),
|
||||
.PCIN(48'b0),
|
||||
.CARRYIN(1'b0)
|
||||
);
|
||||
assign Y = P_48;
|
||||
endmodule
|
||||
|
||||
|
|
@ -1,223 +0,0 @@
|
|||
module RAMB8BWER (
|
||||
(* clkbuf_sink *)
|
||||
input CLKAWRCLK,
|
||||
(* clkbuf_sink *)
|
||||
input CLKBRDCLK,
|
||||
input ENAWREN,
|
||||
input ENBRDEN,
|
||||
input REGCEA,
|
||||
input REGCEBREGCE,
|
||||
input RSTA,
|
||||
input RSTBRST,
|
||||
|
||||
input [12:0] ADDRAWRADDR,
|
||||
input [12:0] ADDRBRDADDR,
|
||||
input [15:0] DIADI,
|
||||
input [15:0] DIBDI,
|
||||
input [1:0] DIPADIP,
|
||||
input [1:0] DIPBDIP,
|
||||
input [1:0] WEAWEL,
|
||||
input [1:0] WEBWEU,
|
||||
|
||||
/* (* abc9_arrival=<TODO> *) */
|
||||
output [15:0] DOADO,
|
||||
/* (* abc9_arrival=<TODO> *) */
|
||||
output [15:0] DOBDO,
|
||||
/* (* abc9_arrival=<TODO> *) */
|
||||
output [1:0] DOPADOP,
|
||||
/* (* abc9_arrival=<TODO> *) */
|
||||
output [1:0] DOPBDOP
|
||||
);
|
||||
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
|
||||
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
|
||||
parameter RAM_MODE = "TDP";
|
||||
parameter integer DOA_REG = 0;
|
||||
parameter integer DOB_REG = 0;
|
||||
|
||||
parameter integer DATA_WIDTH_A = 0;
|
||||
parameter integer DATA_WIDTH_B = 0;
|
||||
|
||||
parameter WRITE_MODE_A = "WRITE_FIRST";
|
||||
parameter WRITE_MODE_B = "WRITE_FIRST";
|
||||
|
||||
parameter EN_RSTRAM_A = "TRUE";
|
||||
parameter EN_RSTRAM_B = "TRUE";
|
||||
|
||||
parameter INIT_A = 18'h000000000;
|
||||
parameter INIT_B = 18'h000000000;
|
||||
parameter SRVAL_A = 18'h000000000;
|
||||
parameter SRVAL_B = 18'h000000000;
|
||||
|
||||
parameter RST_PRIORITY_A = "CE";
|
||||
parameter RST_PRIORITY_B = "CE";
|
||||
|
||||
parameter RSTTYPE = "SYNC";
|
||||
|
||||
parameter SIM_COLLISION_CHECK = "ALL";
|
||||
endmodule
|
||||
|
||||
module RAMB16BWER (
|
||||
(* clkbuf_sink *)
|
||||
input CLKA,
|
||||
(* clkbuf_sink *)
|
||||
input CLKB,
|
||||
input ENA,
|
||||
input ENB,
|
||||
input REGCEA,
|
||||
input REGCEB,
|
||||
input RSTA,
|
||||
input RSTB,
|
||||
|
||||
input [13:0] ADDRA,
|
||||
input [13:0] ADDRB,
|
||||
input [31:0] DIA,
|
||||
input [31:0] DIB,
|
||||
input [3:0] DIPA,
|
||||
input [3:0] DIPB,
|
||||
input [3:0] WEA,
|
||||
input [3:0] WEB,
|
||||
|
||||
/* (* abc9_arrival=<TODO> *) */
|
||||
output [31:0] DOA,
|
||||
/* (* abc9_arrival=<TODO> *) */
|
||||
output [31:0] DOB,
|
||||
/* (* abc9_arrival=<TODO> *) */
|
||||
output [3:0] DOPA,
|
||||
/* (* abc9_arrival=<TODO> *) */
|
||||
output [3:0] DOPB
|
||||
);
|
||||
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
|
||||
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
|
||||
parameter integer DOA_REG = 0;
|
||||
parameter integer DOB_REG = 0;
|
||||
|
||||
parameter integer DATA_WIDTH_A = 0;
|
||||
parameter integer DATA_WIDTH_B = 0;
|
||||
|
||||
parameter WRITE_MODE_A = "WRITE_FIRST";
|
||||
parameter WRITE_MODE_B = "WRITE_FIRST";
|
||||
|
||||
parameter EN_RSTRAM_A = "TRUE";
|
||||
parameter EN_RSTRAM_B = "TRUE";
|
||||
|
||||
parameter INIT_A = 36'h000000000;
|
||||
parameter INIT_B = 36'h000000000;
|
||||
parameter SRVAL_A = 36'h000000000;
|
||||
parameter SRVAL_B = 36'h000000000;
|
||||
|
||||
parameter RST_PRIORITY_A = "CE";
|
||||
parameter RST_PRIORITY_B = "CE";
|
||||
|
||||
parameter RSTTYPE = "SYNC";
|
||||
|
||||
parameter SIM_COLLISION_CHECK = "ALL";
|
||||
endmodule
|
||||
|
||||
File diff suppressed because it is too large
Load diff
35
techlibs/xilinx/xc6s_dsp_map.v
Normal file
35
techlibs/xilinx/xc6s_dsp_map.v
Normal file
|
|
@ -0,0 +1,35 @@
|
|||
module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y);
|
||||
parameter A_SIGNED = 0;
|
||||
parameter B_SIGNED = 0;
|
||||
parameter A_WIDTH = 0;
|
||||
parameter B_WIDTH = 0;
|
||||
parameter Y_WIDTH = 0;
|
||||
|
||||
wire [47:0] P_48;
|
||||
DSP48A1 #(
|
||||
// Disable all registers
|
||||
.A0REG(0),
|
||||
.A1REG(0),
|
||||
.B0REG(0),
|
||||
.B1REG(0),
|
||||
.CARRYINREG(0),
|
||||
.CARRYINSEL("OPMODE5"),
|
||||
.CREG(0),
|
||||
.DREG(0),
|
||||
.MREG(0),
|
||||
.OPMODEREG(0),
|
||||
.PREG(0)
|
||||
) _TECHMAP_REPLACE_ (
|
||||
//Data path
|
||||
.A(A),
|
||||
.B(B),
|
||||
.C(48'b0),
|
||||
.D(18'b0),
|
||||
.P(P_48),
|
||||
|
||||
.OPMODE(8'b0000010)
|
||||
);
|
||||
assign Y = P_48;
|
||||
endmodule
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -1,349 +0,0 @@
|
|||
// Max delays from https://github.com/SymbiFlow/prjxray-db/blob/f8e0364116b2983ac72a3dc8c509ea1cc79e2e3d/artix7/timings/BRAM_L.sdf#L138-L147
|
||||
|
||||
module RAMB18E1 (
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_CLKARDCLK_INVERTED" *)
|
||||
input CLKARDCLK,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_CLKBWRCLK_INVERTED" *)
|
||||
input CLKBWRCLK,
|
||||
(* invertible_pin = "IS_ENARDEN_INVERTED" *)
|
||||
input ENARDEN,
|
||||
(* invertible_pin = "IS_ENBWREN_INVERTED" *)
|
||||
input ENBWREN,
|
||||
input REGCEAREGCE,
|
||||
input REGCEB,
|
||||
(* invertible_pin = "IS_RSTRAMARSTRAM_INVERTED" *)
|
||||
input RSTRAMARSTRAM,
|
||||
(* invertible_pin = "IS_RSTRAMB_INVERTED" *)
|
||||
input RSTRAMB,
|
||||
(* invertible_pin = "IS_RSTREGARSTREG_INVERTED" *)
|
||||
input RSTREGARSTREG,
|
||||
(* invertible_pin = "IS_RSTREGB_INVERTED" *)
|
||||
input RSTREGB,
|
||||
|
||||
input [13:0] ADDRARDADDR,
|
||||
input [13:0] ADDRBWRADDR,
|
||||
input [15:0] DIADI,
|
||||
input [15:0] DIBDI,
|
||||
input [1:0] DIPADIP,
|
||||
input [1:0] DIPBDIP,
|
||||
input [1:0] WEA,
|
||||
input [3:0] WEBWE,
|
||||
|
||||
(* abc9_arrival=2454 *)
|
||||
output [15:0] DOADO,
|
||||
(* abc9_arrival=2454 *)
|
||||
output [15:0] DOBDO,
|
||||
(* abc9_arrival=2454 *)
|
||||
output [1:0] DOPADOP,
|
||||
(* abc9_arrival=2454 *)
|
||||
output [1:0] DOPBDOP
|
||||
);
|
||||
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
|
||||
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
|
||||
parameter IS_CLKARDCLK_INVERTED = 1'b0;
|
||||
parameter IS_CLKBWRCLK_INVERTED = 1'b0;
|
||||
parameter IS_ENARDEN_INVERTED = 1'b0;
|
||||
parameter IS_ENBWREN_INVERTED = 1'b0;
|
||||
parameter IS_RSTRAMARSTRAM_INVERTED = 1'b0;
|
||||
parameter IS_RSTRAMB_INVERTED = 1'b0;
|
||||
parameter IS_RSTREGARSTREG_INVERTED = 1'b0;
|
||||
parameter IS_RSTREGB_INVERTED = 1'b0;
|
||||
|
||||
parameter RAM_MODE = "TDP";
|
||||
parameter integer DOA_REG = 0;
|
||||
parameter integer DOB_REG = 0;
|
||||
|
||||
parameter integer READ_WIDTH_A = 0;
|
||||
parameter integer READ_WIDTH_B = 0;
|
||||
parameter integer WRITE_WIDTH_A = 0;
|
||||
parameter integer WRITE_WIDTH_B = 0;
|
||||
|
||||
parameter WRITE_MODE_A = "WRITE_FIRST";
|
||||
parameter WRITE_MODE_B = "WRITE_FIRST";
|
||||
|
||||
parameter SIM_DEVICE = "VIRTEX6";
|
||||
endmodule
|
||||
|
||||
module RAMB36E1 (
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_CLKARDCLK_INVERTED" *)
|
||||
input CLKARDCLK,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_CLKBWRCLK_INVERTED" *)
|
||||
input CLKBWRCLK,
|
||||
(* invertible_pin = "IS_ENARDEN_INVERTED" *)
|
||||
input ENARDEN,
|
||||
(* invertible_pin = "IS_ENBWREN_INVERTED" *)
|
||||
input ENBWREN,
|
||||
input REGCEAREGCE,
|
||||
input REGCEB,
|
||||
(* invertible_pin = "IS_RSTRAMARSTRAM_INVERTED" *)
|
||||
input RSTRAMARSTRAM,
|
||||
(* invertible_pin = "IS_RSTRAMB_INVERTED" *)
|
||||
input RSTRAMB,
|
||||
(* invertible_pin = "IS_RSTREGARSTREG_INVERTED" *)
|
||||
input RSTREGARSTREG,
|
||||
(* invertible_pin = "IS_RSTREGB_INVERTED" *)
|
||||
input RSTREGB,
|
||||
|
||||
input [15:0] ADDRARDADDR,
|
||||
input [15:0] ADDRBWRADDR,
|
||||
input [31:0] DIADI,
|
||||
input [31:0] DIBDI,
|
||||
input [3:0] DIPADIP,
|
||||
input [3:0] DIPBDIP,
|
||||
input [3:0] WEA,
|
||||
input [7:0] WEBWE,
|
||||
|
||||
(* abc9_arrival=2454 *)
|
||||
output [31:0] DOADO,
|
||||
(* abc9_arrival=2454 *)
|
||||
output [31:0] DOBDO,
|
||||
(* abc9_arrival=2454 *)
|
||||
output [3:0] DOPADOP,
|
||||
(* abc9_arrival=2454 *)
|
||||
output [3:0] DOPBDOP
|
||||
);
|
||||
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
|
||||
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
|
||||
parameter IS_CLKARDCLK_INVERTED = 1'b0;
|
||||
parameter IS_CLKBWRCLK_INVERTED = 1'b0;
|
||||
parameter IS_ENARDEN_INVERTED = 1'b0;
|
||||
parameter IS_ENBWREN_INVERTED = 1'b0;
|
||||
parameter IS_RSTRAMARSTRAM_INVERTED = 1'b0;
|
||||
parameter IS_RSTRAMB_INVERTED = 1'b0;
|
||||
parameter IS_RSTREGARSTREG_INVERTED = 1'b0;
|
||||
parameter IS_RSTREGB_INVERTED = 1'b0;
|
||||
|
||||
parameter RAM_MODE = "TDP";
|
||||
parameter integer DOA_REG = 0;
|
||||
parameter integer DOB_REG = 0;
|
||||
|
||||
parameter integer READ_WIDTH_A = 0;
|
||||
parameter integer READ_WIDTH_B = 0;
|
||||
parameter integer WRITE_WIDTH_A = 0;
|
||||
parameter integer WRITE_WIDTH_B = 0;
|
||||
|
||||
parameter WRITE_MODE_A = "WRITE_FIRST";
|
||||
parameter WRITE_MODE_B = "WRITE_FIRST";
|
||||
|
||||
parameter SIM_DEVICE = "VIRTEX6";
|
||||
endmodule
|
||||
File diff suppressed because it is too large
Load diff
384
techlibs/xilinx/xcu_brams_map.v
Normal file
384
techlibs/xilinx/xcu_brams_map.v
Normal file
|
|
@ -0,0 +1,384 @@
|
|||
module \$__XILINX_RAMB36_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
|
||||
parameter CLKPOL2 = 1;
|
||||
parameter CLKPOL3 = 1;
|
||||
parameter [36863:0] INIT = 36864'bx;
|
||||
|
||||
input CLK2;
|
||||
input CLK3;
|
||||
|
||||
input [8:0] A1ADDR;
|
||||
output [71:0] A1DATA;
|
||||
input A1EN;
|
||||
|
||||
input [8:0] B1ADDR;
|
||||
input [71:0] B1DATA;
|
||||
input [7:0] B1EN;
|
||||
|
||||
wire [15:0] A1ADDR_16 = {A1ADDR, 6'b0};
|
||||
wire [15:0] B1ADDR_16 = {B1ADDR, 6'b0};
|
||||
|
||||
wire [7:0] DIP, DOP;
|
||||
wire [63:0] DI, DO;
|
||||
|
||||
assign A1DATA = { DOP[7], DO[63:56], DOP[6], DO[55:48], DOP[5], DO[47:40], DOP[4], DO[39:32],
|
||||
DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
|
||||
|
||||
assign { DIP[7], DI[63:56], DIP[6], DI[55:48], DIP[5], DI[47:40], DIP[4], DI[39:32],
|
||||
DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
|
||||
|
||||
RAMB36E2 #(
|
||||
.READ_WIDTH_A(72),
|
||||
.WRITE_WIDTH_B(72),
|
||||
.WRITE_MODE_A("READ_FIRST"),
|
||||
.WRITE_MODE_B("READ_FIRST"),
|
||||
.DOA_REG(0),
|
||||
.DOB_REG(0),
|
||||
.IS_CLKARDCLK_INVERTED(!CLKPOL2),
|
||||
.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
|
||||
`include "brams_init_36.vh"
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DOUTBDOUT(DO[63:32]),
|
||||
.DOUTADOUT(DO[31:0]),
|
||||
.DOUTPBDOUTP(DOP[7:4]),
|
||||
.DOUTPADOUTP(DOP[3:0]),
|
||||
.DINBDIN(DI[63:32]),
|
||||
.DINADIN(DI[31:0]),
|
||||
.DINPBDINP(DIP[7:4]),
|
||||
.DINPADINP(DIP[3:0]),
|
||||
|
||||
.ADDRARDADDR(A1ADDR_16),
|
||||
.CLKARDCLK(CLK2),
|
||||
.ENARDEN(A1EN),
|
||||
.ADDRENA(|1),
|
||||
.REGCEAREGCE(|1),
|
||||
.RSTRAMARSTRAM(|0),
|
||||
.RSTREGARSTREG(|0),
|
||||
.WEA(4'b0),
|
||||
|
||||
.ADDRBWRADDR(B1ADDR_16),
|
||||
.CLKBWRCLK(CLK3),
|
||||
.ENBWREN(|1),
|
||||
.ADDRENB(|1),
|
||||
.REGCEB(|1),
|
||||
.RSTRAMB(|0),
|
||||
.RSTREGB(|0),
|
||||
.WEBWE(B1EN),
|
||||
|
||||
.SLEEP(|0)
|
||||
);
|
||||
endmodule
|
||||
|
||||
// ------------------------------------------------------------------------
|
||||
|
||||
module \$__XILINX_RAMB18_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
|
||||
parameter CLKPOL2 = 1;
|
||||
parameter CLKPOL3 = 1;
|
||||
parameter [18431:0] INIT = 18432'bx;
|
||||
|
||||
input CLK2;
|
||||
input CLK3;
|
||||
|
||||
input [8:0] A1ADDR;
|
||||
output [35:0] A1DATA;
|
||||
input A1EN;
|
||||
|
||||
input [8:0] B1ADDR;
|
||||
input [35:0] B1DATA;
|
||||
input [3:0] B1EN;
|
||||
|
||||
wire [13:0] A1ADDR_14 = {A1ADDR, 5'b0};
|
||||
wire [13:0] B1ADDR_14 = {B1ADDR, 5'b0};
|
||||
|
||||
wire [3:0] DIP, DOP;
|
||||
wire [31:0] DI, DO;
|
||||
|
||||
assign A1DATA = { DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
|
||||
assign { DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
|
||||
|
||||
RAMB18E2 #(
|
||||
.READ_WIDTH_A(36),
|
||||
.WRITE_WIDTH_B(36),
|
||||
.WRITE_MODE_A("READ_FIRST"),
|
||||
.WRITE_MODE_B("READ_FIRST"),
|
||||
.DOA_REG(0),
|
||||
.DOB_REG(0),
|
||||
.IS_CLKARDCLK_INVERTED(!CLKPOL2),
|
||||
.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
|
||||
`include "brams_init_18.vh"
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DOUTBDOUT(DO[31:16]),
|
||||
.DOUTADOUT(DO[15:0]),
|
||||
.DOUTPBDOUTP(DOP[3:2]),
|
||||
.DOUTPADOUTP(DOP[1:0]),
|
||||
.DINBDIN(DI[31:16]),
|
||||
.DINADIN(DI[15:0]),
|
||||
.DINPBDINP(DIP[3:2]),
|
||||
.DINPADINP(DIP[1:0]),
|
||||
|
||||
.ADDRARDADDR(A1ADDR_14),
|
||||
.CLKARDCLK(CLK2),
|
||||
.ENARDEN(A1EN),
|
||||
.ADDRENA(|1),
|
||||
.REGCEAREGCE(|1),
|
||||
.RSTRAMARSTRAM(|0),
|
||||
.RSTREGARSTREG(|0),
|
||||
.WEA(2'b0),
|
||||
|
||||
.ADDRBWRADDR(B1ADDR_14),
|
||||
.CLKBWRCLK(CLK3),
|
||||
.ENBWREN(|1),
|
||||
.ADDRENB(|1),
|
||||
.REGCEB(|1),
|
||||
.RSTRAMB(|0),
|
||||
.RSTREGB(|0),
|
||||
.WEBWE(B1EN),
|
||||
|
||||
.SLEEP(|0)
|
||||
);
|
||||
endmodule
|
||||
|
||||
// ------------------------------------------------------------------------
|
||||
|
||||
module \$__XILINX_RAMB36_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
|
||||
parameter CFG_ABITS = 10;
|
||||
parameter CFG_DBITS = 36;
|
||||
parameter CFG_ENABLE_B = 4;
|
||||
|
||||
parameter CLKPOL2 = 1;
|
||||
parameter CLKPOL3 = 1;
|
||||
parameter [36863:0] INIT = 36864'bx;
|
||||
|
||||
input CLK2;
|
||||
input CLK3;
|
||||
|
||||
input [CFG_ABITS-1:0] A1ADDR;
|
||||
output [CFG_DBITS-1:0] A1DATA;
|
||||
input A1EN;
|
||||
|
||||
input [CFG_ABITS-1:0] B1ADDR;
|
||||
input [CFG_DBITS-1:0] B1DATA;
|
||||
input [CFG_ENABLE_B-1:0] B1EN;
|
||||
|
||||
wire [15:0] A1ADDR_16 = A1ADDR << (15 - CFG_ABITS);
|
||||
wire [15:0] B1ADDR_16 = B1ADDR << (15 - CFG_ABITS);
|
||||
wire [7:0] B1EN_8 = B1EN;
|
||||
|
||||
wire [3:0] DIP, DOP;
|
||||
wire [31:0] DI, DO;
|
||||
|
||||
wire [31:0] DOBDO;
|
||||
wire [3:0] DOPBDOP;
|
||||
|
||||
assign A1DATA = { DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
|
||||
assign { DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
|
||||
|
||||
generate if (CFG_DBITS > 8) begin
|
||||
RAMB36E2 #(
|
||||
.READ_WIDTH_A(CFG_DBITS),
|
||||
.READ_WIDTH_B(CFG_DBITS),
|
||||
.WRITE_WIDTH_A(CFG_DBITS),
|
||||
.WRITE_WIDTH_B(CFG_DBITS),
|
||||
.WRITE_MODE_A("READ_FIRST"),
|
||||
.WRITE_MODE_B("READ_FIRST"),
|
||||
.DOA_REG(0),
|
||||
.DOB_REG(0),
|
||||
.IS_CLKARDCLK_INVERTED(!CLKPOL2),
|
||||
.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
|
||||
`include "brams_init_36.vh"
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DINADIN(32'hFFFFFFFF),
|
||||
.DINPADINP(4'hF),
|
||||
.DOUTADOUT(DO[31:0]),
|
||||
.DOUTPADOUTP(DOP[3:0]),
|
||||
.ADDRARDADDR(A1ADDR_16),
|
||||
.CLKARDCLK(CLK2),
|
||||
.ENARDEN(A1EN),
|
||||
.ADDRENA(|1),
|
||||
.REGCEAREGCE(|1),
|
||||
.RSTRAMARSTRAM(|0),
|
||||
.RSTREGARSTREG(|0),
|
||||
.WEA(4'b0),
|
||||
|
||||
.DINBDIN(DI),
|
||||
.DINPBDINP(DIP),
|
||||
.DOUTBDOUT(DOBDO),
|
||||
.DOUTPBDOUTP(DOPBDOP),
|
||||
.ADDRBWRADDR(B1ADDR_16),
|
||||
.CLKBWRCLK(CLK3),
|
||||
.ENBWREN(|1),
|
||||
.ADDRENB(|1),
|
||||
.REGCEB(|0),
|
||||
.RSTRAMB(|0),
|
||||
.RSTREGB(|0),
|
||||
.WEBWE(B1EN_8),
|
||||
|
||||
.SLEEP(|0)
|
||||
);
|
||||
end else begin
|
||||
RAMB36E2 #(
|
||||
.READ_WIDTH_A(CFG_DBITS),
|
||||
.READ_WIDTH_B(CFG_DBITS),
|
||||
.WRITE_WIDTH_A(CFG_DBITS),
|
||||
.WRITE_WIDTH_B(CFG_DBITS),
|
||||
.WRITE_MODE_A("READ_FIRST"),
|
||||
.WRITE_MODE_B("READ_FIRST"),
|
||||
.DOA_REG(0),
|
||||
.DOB_REG(0),
|
||||
.IS_CLKARDCLK_INVERTED(!CLKPOL2),
|
||||
.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
|
||||
`include "brams_init_32.vh"
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DINADIN(32'hFFFFFFFF),
|
||||
.DINPADINP(4'hF),
|
||||
.DOUTADOUT(DO[31:0]),
|
||||
.DOUTPADOUTP(DOP[3:0]),
|
||||
.ADDRARDADDR(A1ADDR_16),
|
||||
.CLKARDCLK(CLK2),
|
||||
.ENARDEN(A1EN),
|
||||
.ADDRENA(|1),
|
||||
.REGCEAREGCE(|1),
|
||||
.RSTRAMARSTRAM(|0),
|
||||
.RSTREGARSTREG(|0),
|
||||
.WEA(4'b0),
|
||||
|
||||
.DINBDIN(DI),
|
||||
.DINPBDINP(DIP),
|
||||
.DOUTBDOUT(DOBDO),
|
||||
.DOUTPBDOUTP(DOPBDOP),
|
||||
.ADDRBWRADDR(B1ADDR_16),
|
||||
.CLKBWRCLK(CLK3),
|
||||
.ENBWREN(|1),
|
||||
.ADDRENB(|1),
|
||||
.REGCEB(|0),
|
||||
.RSTRAMB(|0),
|
||||
.RSTREGB(|0),
|
||||
.WEBWE(B1EN_8),
|
||||
|
||||
.SLEEP(|0)
|
||||
);
|
||||
end endgenerate
|
||||
endmodule
|
||||
|
||||
// ------------------------------------------------------------------------
|
||||
|
||||
module \$__XILINX_RAMB18_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
|
||||
parameter CFG_ABITS = 10;
|
||||
parameter CFG_DBITS = 18;
|
||||
parameter CFG_ENABLE_B = 2;
|
||||
|
||||
parameter CLKPOL2 = 1;
|
||||
parameter CLKPOL3 = 1;
|
||||
parameter [18431:0] INIT = 18432'bx;
|
||||
|
||||
input CLK2;
|
||||
input CLK3;
|
||||
|
||||
input [CFG_ABITS-1:0] A1ADDR;
|
||||
output [CFG_DBITS-1:0] A1DATA;
|
||||
input A1EN;
|
||||
|
||||
input [CFG_ABITS-1:0] B1ADDR;
|
||||
input [CFG_DBITS-1:0] B1DATA;
|
||||
input [CFG_ENABLE_B-1:0] B1EN;
|
||||
|
||||
wire [13:0] A1ADDR_14 = A1ADDR << (14 - CFG_ABITS);
|
||||
wire [13:0] B1ADDR_14 = B1ADDR << (14 - CFG_ABITS);
|
||||
wire [3:0] B1EN_4 = B1EN;
|
||||
|
||||
wire [1:0] DIP, DOP;
|
||||
wire [15:0] DI, DO;
|
||||
|
||||
wire [15:0] DOBDO;
|
||||
wire [1:0] DOPBDOP;
|
||||
|
||||
assign A1DATA = { DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
|
||||
assign { DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
|
||||
|
||||
generate if (CFG_DBITS > 8) begin
|
||||
RAMB18E2 #(
|
||||
.READ_WIDTH_A(CFG_DBITS),
|
||||
.READ_WIDTH_B(CFG_DBITS),
|
||||
.WRITE_WIDTH_A(CFG_DBITS),
|
||||
.WRITE_WIDTH_B(CFG_DBITS),
|
||||
.WRITE_MODE_A("READ_FIRST"),
|
||||
.WRITE_MODE_B("READ_FIRST"),
|
||||
.DOA_REG(0),
|
||||
.DOB_REG(0),
|
||||
.IS_CLKARDCLK_INVERTED(!CLKPOL2),
|
||||
.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
|
||||
`include "brams_init_18.vh"
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DINADIN(16'hFFFF),
|
||||
.DINPADINP(2'b11),
|
||||
.DOUTADOUT(DO),
|
||||
.DOUTPADOUTP(DOP),
|
||||
.ADDRARDADDR(A1ADDR_14),
|
||||
.CLKARDCLK(CLK2),
|
||||
.ENARDEN(A1EN),
|
||||
.ADDRENA(|1),
|
||||
.REGCEAREGCE(|1),
|
||||
.RSTRAMARSTRAM(|0),
|
||||
.RSTREGARSTREG(|0),
|
||||
.WEA(2'b0),
|
||||
|
||||
.DINBDIN(DI),
|
||||
.DINPBDINP(DIP),
|
||||
.DOUTBDOUT(DOBDO),
|
||||
.DOUTPBDOUTP(DOPBDOP),
|
||||
.ADDRBWRADDR(B1ADDR_14),
|
||||
.CLKBWRCLK(CLK3),
|
||||
.ENBWREN(|1),
|
||||
.ADDRENB(|1),
|
||||
.REGCEB(|0),
|
||||
.RSTRAMB(|0),
|
||||
.RSTREGB(|0),
|
||||
.WEBWE(B1EN_4),
|
||||
|
||||
.SLEEP(|0)
|
||||
);
|
||||
end else begin
|
||||
RAMB18E2 #(
|
||||
//.RAM_MODE("TDP"),
|
||||
.READ_WIDTH_A(CFG_DBITS),
|
||||
.READ_WIDTH_B(CFG_DBITS),
|
||||
.WRITE_WIDTH_A(CFG_DBITS),
|
||||
.WRITE_WIDTH_B(CFG_DBITS),
|
||||
.WRITE_MODE_A("READ_FIRST"),
|
||||
.WRITE_MODE_B("READ_FIRST"),
|
||||
.DOA_REG(0),
|
||||
.DOB_REG(0),
|
||||
.IS_CLKARDCLK_INVERTED(!CLKPOL2),
|
||||
.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
|
||||
`include "brams_init_16.vh"
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DINADIN(16'hFFFF),
|
||||
.DINPADINP(2'b11),
|
||||
.DOUTADOUT(DO),
|
||||
.DOUTPADOUTP(DOP),
|
||||
.ADDRARDADDR(A1ADDR_14),
|
||||
.CLKARDCLK(CLK2),
|
||||
.ENARDEN(A1EN),
|
||||
.ADDRENA(|1),
|
||||
.REGCEAREGCE(|1),
|
||||
.RSTRAMARSTRAM(|0),
|
||||
.RSTREGARSTREG(|0),
|
||||
.WEA(2'b0),
|
||||
|
||||
.DINBDIN(DI),
|
||||
.DINPBDINP(DIP),
|
||||
.DOUTBDOUT(DOBDO),
|
||||
.DOUTPBDOUTP(DOPBDOP),
|
||||
.ADDRBWRADDR(B1ADDR_14),
|
||||
.CLKBWRCLK(CLK3),
|
||||
.ENBWREN(|1),
|
||||
.ADDRENB(|1),
|
||||
.REGCEB(|0),
|
||||
.RSTRAMB(|0),
|
||||
.RSTREGB(|0),
|
||||
.WEBWE(B1EN_4),
|
||||
|
||||
.SLEEP(|0)
|
||||
);
|
||||
end endgenerate
|
||||
endmodule
|
||||
|
||||
File diff suppressed because it is too large
Load diff
51
techlibs/xilinx/xcu_dsp_map.v
Normal file
51
techlibs/xilinx/xcu_dsp_map.v
Normal file
|
|
@ -0,0 +1,51 @@
|
|||
module \$__MUL27X18 (input [26:0] A, input [17:0] B, output [44:0] Y);
|
||||
parameter A_SIGNED = 0;
|
||||
parameter B_SIGNED = 0;
|
||||
parameter A_WIDTH = 0;
|
||||
parameter B_WIDTH = 0;
|
||||
parameter Y_WIDTH = 0;
|
||||
|
||||
wire [47:0] P_48;
|
||||
DSP48E2 #(
|
||||
// Disable all registers
|
||||
.ACASCREG(0),
|
||||
.ADREG(0),
|
||||
.A_INPUT("DIRECT"),
|
||||
.ALUMODEREG(0),
|
||||
.AREG(0),
|
||||
.BCASCREG(0),
|
||||
.B_INPUT("DIRECT"),
|
||||
.BREG(0),
|
||||
.CARRYINREG(0),
|
||||
.CARRYINSELREG(0),
|
||||
.CREG(0),
|
||||
.DREG(0),
|
||||
.INMODEREG(0),
|
||||
.MREG(0),
|
||||
.OPMODEREG(0),
|
||||
.PREG(0),
|
||||
.USE_MULT("MULTIPLY"),
|
||||
.USE_SIMD("ONE48"),
|
||||
.AMULTSEL("A"),
|
||||
.BMULTSEL("B")
|
||||
) _TECHMAP_REPLACE_ (
|
||||
//Data path
|
||||
.A({{3{A[26]}}, A}),
|
||||
.B(B),
|
||||
.C(48'b0),
|
||||
.D(27'b0),
|
||||
.P(P_48),
|
||||
|
||||
.INMODE(5'b00000),
|
||||
.ALUMODE(4'b0000),
|
||||
.OPMODE(9'b00000101),
|
||||
.CARRYINSEL(3'b000),
|
||||
|
||||
.ACIN(30'b0),
|
||||
.BCIN(18'b0),
|
||||
.PCIN(48'b0),
|
||||
.CARRYIN(1'b0)
|
||||
);
|
||||
assign Y = P_48;
|
||||
endmodule
|
||||
|
||||
19
techlibs/xilinx/xcup_urams.txt
Normal file
19
techlibs/xilinx/xcup_urams.txt
Normal file
|
|
@ -0,0 +1,19 @@
|
|||
bram $__XILINX_URAM288
|
||||
init 0
|
||||
abits 12
|
||||
dbits 72
|
||||
groups 2
|
||||
ports 1 1
|
||||
wrmode 0 1
|
||||
enable 1 9
|
||||
transp 0 0
|
||||
clocks 2 2
|
||||
clkpol 2 2
|
||||
endbram
|
||||
|
||||
match $__XILINX_URAM288
|
||||
min bits 131072
|
||||
min efficiency 15
|
||||
shuffle_enable B
|
||||
make_transp
|
||||
endmatch
|
||||
47
techlibs/xilinx/xcup_urams_map.v
Normal file
47
techlibs/xilinx/xcup_urams_map.v
Normal file
|
|
@ -0,0 +1,47 @@
|
|||
module \$__XILINX_URAM288 (CLK2, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
|
||||
parameter CLKPOL2 = 1;
|
||||
|
||||
input CLK2;
|
||||
|
||||
input [11:0] A1ADDR;
|
||||
output [71:0] A1DATA;
|
||||
input A1EN;
|
||||
|
||||
input [11:0] B1ADDR;
|
||||
input [71:0] B1DATA;
|
||||
input [8:0] B1EN;
|
||||
|
||||
|
||||
URAM288 #(
|
||||
.BWE_MODE_A("PARITY_INDEPENDENT"),
|
||||
.BWE_MODE_B("PARITY_INDEPENDENT"),
|
||||
.EN_AUTO_SLEEP_MODE("FALSE"),
|
||||
.IREG_PRE_A("FALSE"),
|
||||
.IREG_PRE_B("FALSE"),
|
||||
.IS_CLK_INVERTED(!CLKPOL2),
|
||||
.OREG_A("FALSE"),
|
||||
.OREG_B("FALSE")
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.ADDR_A({11'b0, A1ADDR}),
|
||||
.BWE_A(9'b0),
|
||||
.DIN_A(72'b0),
|
||||
.EN_A(A1EN),
|
||||
.RDB_WR_A(1'b0),
|
||||
.INJECT_DBITERR_A(1'b0),
|
||||
.INJECT_SBITERR_A(1'b0),
|
||||
.RST_A(1'b0),
|
||||
.DOUT_A(A1DATA),
|
||||
|
||||
.ADDR_B({11'b0, B1ADDR}),
|
||||
.BWE_B(B1EN),
|
||||
.DIN_B(B1DATA),
|
||||
.EN_B(|B1EN),
|
||||
.RDB_WR_B(1'b1),
|
||||
.INJECT_DBITERR_B(1'b0),
|
||||
.INJECT_SBITERR_B(1'b0),
|
||||
.RST_B(1'b0),
|
||||
|
||||
.CLK(CLK2),
|
||||
.SLEEP(1'b0)
|
||||
);
|
||||
endmodule
|
||||
Loading…
Add table
Add a link
Reference in a new issue