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Lofty 2025-06-07 01:25:56 +01:00
parent c7ab9f0300
commit 09dd419183
2 changed files with 10 additions and 8 deletions
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17
techlibs/gatemate/cells_sim.v
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@ -237,7 +237,7 @@ module CC_ODDR #(
endmodule endmodule
(* abc9_box, lib_whitebox *) (* abc9_dff, lib_whitebox *)
module CC_DFF #( module CC_DFF #(
parameter [0:0] CLK_INV = 1'b0, parameter [0:0] CLK_INV = 1'b0,
parameter [0:0] EN_INV = 1'b0, parameter [0:0] EN_INV = 1'b0,
@ -258,7 +258,7 @@ module CC_DFF #(
$setup(D, posedge CLK, 100); $setup(D, posedge CLK, 100);
$setup(EN, posedge CLK, 150); $setup(EN, posedge CLK, 150);
if ((~SR_INV && SR) || (SR_INV && ~SR)) (SR => Q) = 150; //if ((~SR_INV && SR) || (SR_INV && ~SR)) (SR => Q) = 150;
endspecify endspecify
wire clk, en, sr; wire clk, en, sr;
@ -426,21 +426,22 @@ module CC_MX8 (
endmodule endmodule
(* abc9_box, lib_whitebox *) //(* abc9_box, lib_whitebox *)
module CC_ADDF ( module CC_ADDF (
input A, B, (* abc9_carry *) input CI, input A, B, (* abc9_carry *) input CI,
(* abc9_carry *) output CO, output S (* abc9_carry *) output CO, output S
); );
specify specify
(A => CO) = 0; (A => CO) = 1;
(B => CO) = 0; (B => CO) = 1;
(CI => CO) = 0; (CI => CO) = 1;
(A => S) = 484; (A => S) = 484;
(B => S) = 449; (B => S) = 449;
(CI => S) = 0; (CI => S) = 1;
endspecify endspecify
assign {CO, S} = A + B + CI; assign CO = A ^ B ^ CI;
assign S = (A & B) | (A & CI) | (B & CI);
endmodule endmodule

1
techlibs/gatemate/synth_gatemate.cc
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@ -307,6 +307,7 @@ struct SynthGateMatePass : public ScriptPass
if (check_label("map_luts")) if (check_label("map_luts"))
{ {
run("stat");
if (luttree || help_mode) { if (luttree || help_mode) {
std::string abc_args = " -genlib +/gatemate/lut_tree_cells.genlib -script \"+&sweep;&dc2;&nf\""; std::string abc_args = " -genlib +/gatemate/lut_tree_cells.genlib -script \"+&sweep;&dc2;&nf\"";
if (dff) { if (dff) {