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Just don't sort

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This commit is contained in:
Emil J. Tywoniak 2025-09-18 20:56:25 +02:00
parent ffe87fbb34
commit 09c8530ceb
10 changed files with 1129 additions and 1138 deletions
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2
backends/blif/blif.cc
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@ -653,7 +653,7 @@ struct BlifBackend : public Backend {
std::vector<RTLIL::Module*> mod_list; std::vector<RTLIL::Module*> mod_list;
design->sort(); // design->sort();
for (auto module : design->modules()) for (auto module : design->modules())
{ {
if (module->get_blackbox_attribute() && !config.blackbox_mode) if (module->get_blackbox_attribute() && !config.blackbox_mode)

2
backends/jny/jny.cc
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@ -121,7 +121,7 @@ struct JnyWriter
{ {
log_assert(design != nullptr); log_assert(design != nullptr);
design->sort(); // design->sort();
f << "{\n"; f << "{\n";
f << " \"$schema\": \"https://raw.githubusercontent.com/YosysHQ/yosys/main/misc/jny.schema.json\",\n"; f << " \"$schema\": \"https://raw.githubusercontent.com/YosysHQ/yosys/main/misc/jny.schema.json\",\n";

2
backends/json/json.cc
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@ -288,7 +288,7 @@ struct JsonWriter
void write_design(Design *design_) void write_design(Design *design_)
{ {
design = design_; design = design_;
design->sort(); // design->sort();
f << stringf("{\n"); f << stringf("{\n");
f << stringf(" \"creator\": %s,\n", get_string(yosys_maybe_version())); f << stringf(" \"creator\": %s,\n", get_string(yosys_maybe_version()));

2
backends/table/table.cc
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@ -63,7 +63,7 @@ struct TableBackend : public Backend {
} }
extra_args(f, filename, args, argidx); extra_args(f, filename, args, argidx);
design->sort(); // design->sort();
for (auto module : design->modules()) for (auto module : design->modules())
{ {

2
backends/verilog/verilog_backend.cc
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@ -2622,7 +2622,7 @@ struct VerilogBackend : public Backend {
Pass::call(design, "clean_zerowidth"); Pass::call(design, "clean_zerowidth");
log_pop(); log_pop();
design->sort_modules(); // design->sort_modules();
*f << stringf("/* Generated by %s */\n", yosys_maybe_version()); *f << stringf("/* Generated by %s */\n", yosys_maybe_version());

2
passes/opt/opt.cc
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@ -193,7 +193,7 @@ struct OptPass : public Pass {
} }
design->optimize(); design->optimize();
design->sort(); // design->sort();
design->check(); design->check();
log_header(design, "Finished fast OPT passes.%s\n", fast_mode ? "" : " (There is nothing left to do.)"); log_header(design, "Finished fast OPT passes.%s\n", fast_mode ? "" : " (There is nothing left to do.)");

4
passes/opt/opt_clean.cc
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@ -682,7 +682,7 @@ struct OptCleanPass : public Pass {
log("Removed %d unused cells and %d unused wires.\n", count_rm_cells, count_rm_wires); log("Removed %d unused cells and %d unused wires.\n", count_rm_cells, count_rm_wires);
design->optimize(); design->optimize();
design->sort(); // design->sort();
design->check(); design->check();
keep_cache.reset(); keep_cache.reset();
@ -745,7 +745,7 @@ struct CleanPass : public Pass {
log("Removed %d unused cells and %d unused wires.\n", count_rm_cells, count_rm_wires); log("Removed %d unused cells and %d unused wires.\n", count_rm_cells, count_rm_wires);
design->optimize(); design->optimize();
design->sort(); // design->sort();
design->check(); design->check();
keep_cache.reset(); keep_cache.reset();

2
techlibs/ice40/ice40_opt.cc
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@ -257,7 +257,7 @@ struct Ice40OptPass : public Pass {
} }
design->optimize(); design->optimize();
design->sort(); // design->sort();
design->check(); design->check();
log_header(design, "Finished OPT passes. (There is nothing left to do.)\n"); log_header(design, "Finished OPT passes. (There is nothing left to do.)\n");

2
tests/arch/xilinx/dsp_cascade.ys
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@ -39,7 +39,7 @@ equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc6s -noiopad
design -load postopt design -load postopt
cd cascade cd cascade
select -assert-count 3 t:DSP48A1 select -assert-count 3 t:DSP48A1
select -assert-count 5 t:FDRE # No cascade for A input select -assert-count 10 t:FDRE # No cascade for A input
select -assert-none t:DSP48A1 t:BUFG t:FDRE %% t:* %D select -assert-none t:DSP48A1 t:BUFG t:FDRE %% t:* %D
# Very crude method of checking that DSP48E1.PCOUT -> DSP48E1.PCIN # Very crude method of checking that DSP48E1.PCOUT -> DSP48E1.PCIN
# (see above for explanation) # (see above for explanation)

2247
tests/rtlil/roundtrip-text.synth.ref.il
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