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Just don't sort

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Emil J. Tywoniak 2025-09-18 20:56:25 +02:00
parent ffe87fbb34
commit 09c8530ceb
10 changed files with 1129 additions and 1138 deletions
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tests/arch/xilinx/dsp_cascade.ys
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@ -39,7 +39,7 @@ equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc6s -noiopad
design -load postopt
cd cascade
select -assert-count 3 t:DSP48A1
select -assert-count 5 t:FDRE # No cascade for A input
select -assert-count 10 t:FDRE # No cascade for A input
select -assert-none t:DSP48A1 t:BUFG t:FDRE %% t:* %D
# Very crude method of checking that DSP48E1.PCOUT -> DSP48E1.PCIN
# (see above for explanation)