mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-11 02:08:08 +00:00
Code Activity

Just don't sort

Browse source
This commit is contained in:
Emil J. Tywoniak 2025-09-18 20:56:25 +02:00
parent ffe87fbb34
commit 09c8530ceb
10 changed files with 1129 additions and 1138 deletions
Download patch file Download diff file Expand all files Collapse all files

2
backends/verilog/verilog_backend.cc
View file

@ -2622,7 +2622,7 @@ struct VerilogBackend : public Backend {
Pass::call(design, "clean_zerowidth");
log_pop();
design->sort_modules();
// design->sort_modules();
*f << stringf("/* Generated by %s */\n", yosys_maybe_version());