Just don't sort

backends/blif/blif.cc

@@ -653,7 +653,7 @@ struct BlifBackend : public Backend {
 
 		std::vector<RTLIL::Module*> mod_list;
 
-		design->sort();
+		// design->sort();
 		for (auto module : design->modules())
 		{
 			if (module->get_blackbox_attribute() && !config.blackbox_mode)

backends/jny/jny.cc

@@ -121,7 +121,7 @@ struct JnyWriter
     {
         log_assert(design != nullptr);
 
-        design->sort();
+        // design->sort();
 
         f << "{\n";
         f << "  \"$schema\": \"https://raw.githubusercontent.com/YosysHQ/yosys/main/misc/jny.schema.json\",\n";

backends/json/json.cc

@@ -288,7 +288,7 @@ struct JsonWriter
 	void write_design(Design *design_)
 	{
 		design = design_;
-		design->sort();
+		// design->sort();
 
 		f << stringf("{\n");
 		f << stringf("  \"creator\": %s,\n", get_string(yosys_maybe_version()));

backends/table/table.cc

@@ -63,7 +63,7 @@ struct TableBackend : public Backend {
 		}
 		extra_args(f, filename, args, argidx);
 
-		design->sort();
+		// design->sort();
 
 		for (auto module : design->modules())
 		{

backends/verilog/verilog_backend.cc

@@ -2622,7 +2622,7 @@ struct VerilogBackend : public Backend {
 		Pass::call(design, "clean_zerowidth");
 		log_pop();
 
-               design->sort_modules();
+		// design->sort_modules();
 
 		*f << stringf("/* Generated by %s */\n", yosys_maybe_version());
 

passes/opt/opt.cc

@@ -193,7 +193,7 @@ struct OptPass : public Pass {
 		}
 
 		design->optimize();
-		design->sort();
+		// design->sort();
 		design->check();
 
 		log_header(design, "Finished fast OPT passes.%s\n", fast_mode ? "" : " (There is nothing left to do.)");

passes/opt/opt_clean.cc

@@ -682,7 +682,7 @@ struct OptCleanPass : public Pass {
 			log("Removed %d unused cells and %d unused wires.\n", count_rm_cells, count_rm_wires);
 
 		design->optimize();
-		design->sort();
+		// design->sort();
 		design->check();
 
 		keep_cache.reset();
@@ -745,7 +745,7 @@ struct CleanPass : public Pass {
 			log("Removed %d unused cells and %d unused wires.\n", count_rm_cells, count_rm_wires);
 
 		design->optimize();
-		design->sort();
+		// design->sort();
 		design->check();
 
 		keep_cache.reset();

techlibs/ice40/ice40_opt.cc

@@ -257,7 +257,7 @@ struct Ice40OptPass : public Pass {
 		}
 
 		design->optimize();
-		design->sort();
+		// design->sort();
 		design->check();
 
 		log_header(design, "Finished OPT passes. (There is nothing left to do.)\n");

tests/arch/xilinx/dsp_cascade.ys

@@ -39,7 +39,7 @@ equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc6s -noiopad
 design -load postopt
 cd cascade
 select -assert-count 3 t:DSP48A1
-select -assert-count 5 t:FDRE # No cascade for A input
+select -assert-count 10 t:FDRE # No cascade for A input
 select -assert-none t:DSP48A1 t:BUFG t:FDRE %% t:* %D
 # Very crude method of checking that DSP48E1.PCOUT -> DSP48E1.PCIN
 #   (see above for explanation)