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https://github.com/YosysHQ/yosys
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Clang-Format CSA tree.
This commit is contained in:
nella
parent
9374ac325d
commit
09b6b7d24f
1 changed files with 70 additions and 85 deletions
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@ -2,10 +2,10 @@
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* Replaces chains of $add/$sub and $macc cells with carry-save adder trees
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/macc.h"
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#include "kernel/sigtools.h"
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#include "kernel/wallace_tree.h"
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#include "kernel/yosys.h"
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#include <queue>
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@ -18,19 +18,19 @@ struct Operand {
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bool negate;
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};
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struct Traversal
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{
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struct Traversal {
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SigMap sigmap;
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dict<SigBit, pool<Cell*>> bit_consumers;
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dict<SigBit, pool<Cell *>> bit_consumers;
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dict<SigBit, int> fanout;
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Traversal(Module* module) : sigmap(module) {
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Traversal(Module *module) : sigmap(module)
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{
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for (auto cell : module->cells())
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for (auto& conn : cell->connections())
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for (auto &conn : cell->connections())
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if (cell->input(conn.first))
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for (auto bit : sigmap(conn.second))
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bit_consumers[bit].insert(cell);
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for (auto& pair : bit_consumers)
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for (auto &pair : bit_consumers)
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fanout[pair.first] = pair.second.size();
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for (auto wire : module->wires())
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@ -41,30 +41,20 @@ struct Traversal
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};
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struct Cells {
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pool<Cell*> addsub;
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pool<Cell*> alu;
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pool<Cell*> macc;
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pool<Cell *> addsub;
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pool<Cell *> alu;
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pool<Cell *> macc;
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static bool is_addsub(Cell* cell)
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static bool is_addsub(Cell *cell) { return cell->type == ID($add) || cell->type == ID($sub); }
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static bool is_alu(Cell *cell) { return cell->type == ID($alu); }
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static bool is_macc(Cell *cell) { return cell->type == ID($macc) || cell->type == ID($macc_v2); }
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bool empty() { return addsub.empty() && alu.empty() && macc.empty(); }
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Cells(Module *module)
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{
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return cell->type == ID($add) || cell->type == ID($sub);
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}
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static bool is_alu(Cell* cell)
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{
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return cell->type == ID($alu);
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}
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static bool is_macc(Cell* cell)
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{
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return cell->type == ID($macc) || cell->type == ID($macc_v2);
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}
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bool empty() {
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return addsub.empty() && alu.empty() && macc.empty();
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}
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Cells(Module* module) {
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for (auto cell : module->cells()) {
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if (is_addsub(cell))
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addsub.insert(cell);
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@ -77,16 +67,16 @@ struct Cells {
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};
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struct AluInfo {
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Cells& cells;
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Traversal& traversal;
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bool is_subtract(Cell* cell)
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Cells &cells;
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Traversal &traversal;
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bool is_subtract(Cell *cell)
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{
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SigSpec bi = traversal.sigmap(cell->getPort(ID::BI));
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SigSpec ci = traversal.sigmap(cell->getPort(ID::CI));
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return GetSize(bi) == 1 && bi[0] == State::S1 && GetSize(ci) == 1 && ci[0] == State::S1;
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}
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bool is_add(Cell* cell)
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bool is_add(Cell *cell)
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{
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SigSpec bi = traversal.sigmap(cell->getPort(ID::BI));
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SigSpec ci = traversal.sigmap(cell->getPort(ID::CI));
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@ -95,7 +85,7 @@ struct AluInfo {
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// Chainable cells are adds/subs with no carry usage, connected chainable
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// cells form chains that can be replaced with CSA trees.
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bool is_chainable(Cell* cell)
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bool is_chainable(Cell *cell)
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{
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if (!(is_add(cell) || is_subtract(cell)))
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return false;
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@ -111,25 +101,24 @@ struct AluInfo {
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}
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};
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struct Rewriter
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{
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Module* module;
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Cells& cells;
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struct Rewriter {
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Module *module;
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Cells &cells;
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Traversal traversal;
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AluInfo alu_info;
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Rewriter(Module* module, Cells& cells) : module(module), cells(cells), traversal(module), alu_info{cells, traversal} {}
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Rewriter(Module *module, Cells &cells) : module(module), cells(cells), traversal(module), alu_info{cells, traversal} {}
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Cell* sole_chainable_consumer(SigSpec sig, const pool<Cell*>& candidates)
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Cell *sole_chainable_consumer(SigSpec sig, const pool<Cell *> &candidates)
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{
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Cell* consumer = nullptr;
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Cell *consumer = nullptr;
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for (auto bit : sig) {
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if (!traversal.fanout.count(bit) || traversal.fanout[bit] != 1)
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return nullptr;
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if (!traversal.bit_consumers.count(bit) || traversal.bit_consumers[bit].size() != 1)
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return nullptr;
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Cell* c = *traversal.bit_consumers[bit].begin();
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Cell *c = *traversal.bit_consumers[bit].begin();
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if (!candidates.count(c))
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return nullptr;
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@ -142,36 +131,35 @@ struct Rewriter
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}
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// Find cells that consume another cell's output.
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dict<Cell*, Cell*> find_parents(const pool<Cell*>& candidates)
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dict<Cell *, Cell *> find_parents(const pool<Cell *> &candidates)
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{
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dict<Cell*, Cell*> parent_of;
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dict<Cell *, Cell *> parent_of;
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for (auto cell : candidates) {
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Cell* consumer = sole_chainable_consumer(
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traversal.sigmap(cell->getPort(ID::Y)), candidates);
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Cell *consumer = sole_chainable_consumer(traversal.sigmap(cell->getPort(ID::Y)), candidates);
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if (consumer && consumer != cell)
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parent_of[cell] = consumer;
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}
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return parent_of;
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}
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std::pair<dict<Cell*, pool<Cell*>>, pool<Cell*>> invert_parent_map(const dict<Cell*, Cell*>& parent_of)
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std::pair<dict<Cell *, pool<Cell *>>, pool<Cell *>> invert_parent_map(const dict<Cell *, Cell *> &parent_of)
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{
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dict<Cell*, pool<Cell*>> children_of;
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pool<Cell*> has_parent;
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for (auto& [child, parent] : parent_of) {
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dict<Cell *, pool<Cell *>> children_of;
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pool<Cell *> has_parent;
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for (auto &[child, parent] : parent_of) {
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children_of[parent].insert(child);
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has_parent.insert(child);
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}
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return {children_of, has_parent};
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}
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pool<Cell*> collect_chain(Cell* root, const dict<Cell*, pool<Cell*>>& children_of)
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pool<Cell *> collect_chain(Cell *root, const dict<Cell *, pool<Cell *>> &children_of)
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{
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pool<Cell*> chain;
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std::queue<Cell*> q;
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pool<Cell *> chain;
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std::queue<Cell *> q;
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q.push(root);
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while (!q.empty()) {
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Cell* cur = q.front();
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Cell *cur = q.front();
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q.pop();
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if (!chain.insert(cur).second)
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continue;
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@ -183,7 +171,7 @@ struct Rewriter
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return chain;
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}
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pool<SigBit> internal_bits(const pool<Cell*>& chain)
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pool<SigBit> internal_bits(const pool<Cell *> &chain)
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{
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pool<SigBit> bits;
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for (auto cell : chain)
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@ -192,7 +180,7 @@ struct Rewriter
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return bits;
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}
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static bool overlaps(SigSpec sig, const pool<SigBit>& bits)
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static bool overlaps(SigSpec sig, const pool<SigBit> &bits)
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{
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for (auto bit : sig)
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if (bits.count(bit))
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@ -200,7 +188,7 @@ struct Rewriter
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return false;
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}
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bool feeds_subtracted_port(Cell* child, Cell* parent)
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bool feeds_subtracted_port(Cell *child, Cell *parent)
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{
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bool parent_subtracts;
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if (parent->type == ID($sub))
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@ -213,7 +201,7 @@ struct Rewriter
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if (!parent_subtracts)
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return false;
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SigSpec child_y = traversal.sigmap(child->getPort(ID::Y));
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SigSpec child_y = traversal.sigmap(child->getPort(ID::Y));
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SigSpec parent_b = traversal.sigmap(parent->getPort(ID::B));
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for (auto bit : child_y)
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for (auto pbit : parent_b)
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@ -222,20 +210,18 @@ struct Rewriter
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return false;
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}
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std::vector<Operand> extract_chain_operands(
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const pool<Cell*>& chain,
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Cell* root,
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const dict<Cell*, Cell*>& parent_of,
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int& neg_compensation
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) {
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std::vector<Operand> extract_chain_operands(const pool<Cell *> &chain, Cell *root, const dict<Cell *, Cell *> &parent_of,
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int &neg_compensation)
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{
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pool<SigBit> chain_bits = internal_bits(chain);
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dict<Cell*, bool> negated;
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dict<Cell *, bool> negated;
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negated[root] = false;
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{
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std::queue<Cell*> q;
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std::queue<Cell *> q;
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q.push(root);
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while (!q.empty()) {
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Cell* cur = q.front(); q.pop();
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Cell *cur = q.front();
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q.pop();
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for (auto cell : chain) {
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if (!parent_of.count(cell) || parent_of.at(cell) != cur)
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continue;
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@ -266,23 +252,25 @@ struct Rewriter
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if (!overlaps(a, chain_bits)) {
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bool neg = cell_neg;
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operands.push_back({a, a_signed, neg});
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if (neg) neg_compensation++;
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if (neg)
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neg_compensation++;
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}
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if (!overlaps(b, chain_bits)) {
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bool neg = cell_neg ^ b_sub;
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operands.push_back({b, b_signed, neg});
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if (neg) neg_compensation++;
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if (neg)
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neg_compensation++;
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}
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}
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return operands;
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}
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bool extract_macc_operands(Cell* cell, std::vector<Operand>& operands, int& neg_compensation)
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bool extract_macc_operands(Cell *cell, std::vector<Operand> &operands, int &neg_compensation)
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{
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Macc macc(cell);
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neg_compensation = 0;
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for (auto& term : macc.terms) {
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for (auto &term : macc.terms) {
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// Bail on multiplication
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if (GetSize(term.in_b) != 0)
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return false;
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@ -308,17 +296,13 @@ struct Rewriter
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return sig;
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}
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void replace_with_csa_tree(
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std::vector<Operand>& operands,
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SigSpec result_y,
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int neg_compensation,
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const char* desc
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) {
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void replace_with_csa_tree(std::vector<Operand> &operands, SigSpec result_y, int neg_compensation, const char *desc)
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{
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int width = GetSize(result_y);
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std::vector<SigSpec> extended;
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extended.reserve(operands.size() + 1);
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for (auto& op : operands) {
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for (auto &op : operands) {
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SigSpec s = extend_operand(op.sig, op.is_signed, width);
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if (op.negate)
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s = module->Not(NEW_ID, s);
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@ -339,7 +323,7 @@ struct Rewriter
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void process_chains()
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{
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pool<Cell*> candidates;
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pool<Cell *> candidates;
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for (auto cell : cells.addsub)
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candidates.insert(cell);
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for (auto cell : cells.alu)
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@ -352,12 +336,12 @@ struct Rewriter
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auto parent_of = find_parents(candidates);
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auto [children_of, has_parent] = invert_parent_map(parent_of);
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pool<Cell*> processed;
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pool<Cell *> processed;
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for (auto root : candidates) {
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if (has_parent.count(root) || processed.count(root))
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continue; // Not a tree root
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pool<Cell*> chain = collect_chain(root, children_of);
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pool<Cell *> chain = collect_chain(root, children_of);
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if (chain.size() < 2)
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continue;
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@ -391,13 +375,14 @@ struct Rewriter
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}
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};
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void run(Module* module) {
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void run(Module *module)
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{
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Cells cells(module);
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if (cells.empty())
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return;
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Rewriter rewriter {module, cells};
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Rewriter rewriter{module, cells};
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rewriter.process_chains();
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rewriter.process_maccs();
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}
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@ -421,7 +406,7 @@ struct CsaTreePass : public Pass {
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design* design) override
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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log_header(design, "Executing CSA_TREE pass.\n");
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