Merge pull request #150 from Silimate/reenable_vhdl

Reenable VHDL

tests/verific/README.md

@@ -2,8 +2,6 @@
 
 ## Disabled
 
-- `import_warning_operator`: no VHDL
-- `mixed_flist`: no VHDL
 - `memory_semantics`: relies on initial values being retained, which we do not want
 - `rom_case`: we need different behavior for multi-port memories
 - `blackbox*`: we need different behavior for parametrized blackboxes

tests/verific/import_warning_operator.ys

@@ -0,0 +1,5 @@
+logger -expect warning "import_warning_operator.vhd:[0-9]+.[0-9]+-[0-9]+.[0-9]+: Unsupported Verific operator: nor_4 \(fallback to gate level implementation provided by verific\)" 1
+verific -vhdl import_warning_operator.vhd
+verific -import top
+logger -check-expected
+design -reset