mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-06-02 15:18:07 +00:00
Code Activity

Add signed keyword in write_verilog

Browse source
This commit is contained in:
Gus Smith 2026-03-23 15:20:42 -07:00 • committed by nella
parent 4f08486602
commit 0978192b3a
1 changed files with 6 additions and 5 deletions
Download patch file Download diff file Expand all files Collapse all files

11
backends/verilog/verilog_backend.cc
View file

@ -456,21 +456,22 @@ void dump_wire(std::ostream &f, std::string indent, RTLIL::Wire *wire)
if (wire->attributes.count(ID::single_bit_vector)) if (wire->attributes.count(ID::single_bit_vector))
range = stringf(" [%d:%d]", wire->start_offset, wire->start_offset); range = stringf(" [%d:%d]", wire->start_offset, wire->start_offset);
} }
std::string sign = wire->is_signed ? " signed" : "";
if (wire->port_input && !wire->port_output) if (wire->port_input && !wire->port_output)
f << stringf("%s" "input%s %s;\n", indent, range, id(wire->name)); f << stringf("%s" "input%s%s %s;\n", indent, sign, range, id(wire->name));
if (!wire->port_input && wire->port_output) if (!wire->port_input && wire->port_output)
f << stringf("%s" "output%s %s;\n", indent, range, id(wire->name)); f << stringf("%s" "output%s%s %s;\n", indent, sign, range, id(wire->name));
if (wire->port_input && wire->port_output) if (wire->port_input && wire->port_output)
f << stringf("%s" "inout%s %s;\n", indent, range, id(wire->name)); f << stringf("%s" "inout%s%s %s;\n", indent, sign, range, id(wire->name));
if (reg_wires.count(wire->name)) { if (reg_wires.count(wire->name)) {
f << stringf("%s" "reg%s %s", indent, range, id(wire->name)); f << stringf("%s" "reg%s%s %s", indent, sign, range, id(wire->name));
if (wire->attributes.count(ID::init)) { if (wire->attributes.count(ID::init)) {
f << stringf(" = "); f << stringf(" = ");
dump_const(f, wire->attributes.at(ID::init)); dump_const(f, wire->attributes.at(ID::init));
} }
f << stringf(";\n"); f << stringf(";\n");
} else } else
f << stringf("%s" "wire%s %s;\n", indent, range, id(wire->name)); f << stringf("%s" "wire%s%s %s;\n", indent, sign, range, id(wire->name));
#endif #endif
} }