mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-07-22 20:32:07 +00:00
Code Activity

cxxrtl: disambiguate values/wires and their aliases in debug info.

Browse source 
With this change, it is easier to see which signals carry state (only
wire<>s appear as `reg` in VCD files) and to construct a minimal
checkpoint (CXXRTL_WIRE debug items represent the canonical smallest
set of state required to fully reconstruct the simulation).
This commit is contained in:
whitequark 2020-06-10 14:39:45 +00:00
parent 8f1a320646
commit 0955a603c8
4 changed files with 50 additions and 9 deletions
Download patch file Download diff file Expand all files Collapse all files

29
backends/cxxrtl/cxxrtl.h
View file

@ -716,6 +716,9 @@ struct metadata {
typedef std::map<std::string, metadata> metadata_map;
// Helper class to disambiguate values/wires and their aliases.
struct debug_alias {};
// This structure is intended for consumption via foreign function interfaces, like Python's ctypes.
// Because of this it uses a C-style layout that is easy to parse rather than more idiomatic C++.
//
@ -726,6 +729,7 @@ struct debug_item : ::cxxrtl_object {
VALUE = CXXRTL_VALUE,
WIRE = CXXRTL_WIRE,
MEMORY = CXXRTL_MEMORY,
ALIAS = CXXRTL_ALIAS,
};
debug_item(const ::cxxrtl_object &object) : cxxrtl_object(object) {}
@ -748,7 +752,7 @@ struct debug_item : ::cxxrtl_object {
type = VALUE;
width = Bits;
depth = 1;
curr = const_cast<uint32_t*>(item.data);
curr = const_cast<chunk_t*>(item.data);
next = nullptr;
}
@ -774,6 +778,29 @@ struct debug_item : ::cxxrtl_object {
curr = item.data.empty() ? nullptr : item.data[0].data;
next = nullptr;
}
template<size_t Bits>
debug_item(debug_alias, const value<Bits> &item) {
static_assert(sizeof(item) == value<Bits>::chunks * sizeof(chunk_t),
"value<Bits> is not compatible with C layout");
type = ALIAS;
width = Bits;
depth = 1;
curr = const_cast<chunk_t*>(item.data);
next = nullptr;
}
template<size_t Bits>
debug_item(debug_alias, const wire<Bits> &item) {
static_assert(sizeof(item.curr) == value<Bits>::chunks * sizeof(chunk_t) &&
sizeof(item.next) == value<Bits>::chunks * sizeof(chunk_t),
"wire<Bits> is not compatible with C layout");
type = ALIAS;
width = Bits;
depth = 1;
curr = const_cast<chunk_t*>(item.curr.data);
next = nullptr;
}
};
static_assert(std::is_standard_layout<debug_item>::value, "debug_item is not compatible with C layout");