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https://github.com/YosysHQ/yosys
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Major improvements in mem2reg and added "init" sync rules
This commit is contained in:
Clifford Wolf
parent
84ced2bb8e
commit
09471846c5
10 changed files with 379 additions and 93 deletions
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@ -162,12 +162,31 @@ namespace AST
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void delete_children();
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~AstNode();
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enum mem2reg_flags
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{
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/* status flags */
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MEM2REG_FL_ALL = 0x00000001,
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MEM2REG_FL_ASYNC = 0x00000002,
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MEM2REG_FL_INIT = 0x00000004,
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/* candidate flags */
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MEM2REG_FL_FORCED = 0x00000100,
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MEM2REG_FL_SET_INIT = 0x00000200,
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MEM2REG_FL_SET_ELSE = 0x00000400,
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MEM2REG_FL_SET_ASYNC = 0x00000800,
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MEM2REG_FL_EQ2 = 0x00001000,
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/* proc flags */
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MEM2REG_FL_EQ1 = 0x01000000,
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};
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// simplify() creates a simpler AST by unrolling for-loops, expanding generate blocks, etc.
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// it also sets the id2ast pointers so that identifier lookups are fast in genRTLIL()
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bool simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, int width_hint, bool sign_hint);
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void expand_genblock(std::string index_var, std::string prefix, std::map<std::string, std::string> &name_map);
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void replace_ids(std::map<std::string, std::string> &rules);
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void mem2reg_as_needed_pass1(std::set<AstNode*> &mem2reg_set, std::set<AstNode*> &mem2reg_candidates, bool sync_proc, bool async_proc, bool force_mem2reg);
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void mem2reg_as_needed_pass1(std::map<AstNode*, std::set<std::string>> &mem2reg_places,
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std::map<AstNode*, uint32_t> &mem2reg_flags, std::map<AstNode*, uint32_t> &proc_flags, uint32_t &status_flags);
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void mem2reg_as_needed_pass2(std::set<AstNode*> &mem2reg_set, AstNode *mod, AstNode *block);
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void meminfo(int &mem_width, int &mem_size, int &addr_bits);
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@ -234,7 +234,7 @@ struct AST_INTERNAL::ProcessGenerator
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{
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// input and output structures
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AstNode *always;
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RTLIL::SigSpec skipSyncSignals;
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RTLIL::SigSpec initSyncSignals;
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RTLIL::Process *proc;
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const RTLIL::SigSpec &outputSignals;
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@ -258,7 +258,10 @@ struct AST_INTERNAL::ProcessGenerator
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// map helps generating nice numbered names for all this temporary signals.
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std::map<RTLIL::Wire*, int> new_temp_count;
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ProcessGenerator(AstNode *always, RTLIL::SigSpec skipSyncSignalsArg = RTLIL::SigSpec()) : always(always), skipSyncSignals(skipSyncSignalsArg), outputSignals(subst_lvalue_from)
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// Buffer for generating the init action
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RTLIL::SigSpec init_lvalue, init_rvalue;
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ProcessGenerator(AstNode *always, RTLIL::SigSpec initSyncSignalsArg = RTLIL::SigSpec()) : always(always), initSyncSignals(initSyncSignalsArg), outputSignals(subst_lvalue_from)
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{
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// generate process and simple root case
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proc = new RTLIL::Process;
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@ -321,6 +324,25 @@ struct AST_INTERNAL::ProcessGenerator
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for (auto child : always->children)
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if (child->type == AST_BLOCK)
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processAst(child);
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if (initSyncSignals.width > 0)
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{
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RTLIL::SyncRule *sync = new RTLIL::SyncRule;
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sync->type = RTLIL::SyncType::STi;
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proc->syncs.push_back(sync);
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assert(init_lvalue.width == init_rvalue.width);
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init_lvalue.optimize();
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init_rvalue.optimize();
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int offset = 0;
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for (size_t i = 0; i < init_lvalue.chunks.size(); i++) {
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RTLIL::SigSpec lhs = init_lvalue.chunks[i];
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RTLIL::SigSpec rhs = init_rvalue.extract(offset, init_lvalue.chunks[i].width);
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sync->actions.push_back(RTLIL::SigSig(lhs, rhs));
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offset += lhs.width;
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}
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}
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}
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// create new temporary signals
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@ -406,8 +428,11 @@ struct AST_INTERNAL::ProcessGenerator
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// are avoided and the generated $mux cells have a more "natural" size.
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void addChunkActions(std::vector<RTLIL::SigSig> &actions, RTLIL::SigSpec lvalue, RTLIL::SigSpec rvalue, bool inSyncRule = false)
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{
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if (inSyncRule)
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lvalue.remove2(skipSyncSignals, &rvalue);
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if (inSyncRule && initSyncSignals.width > 0) {
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init_lvalue.append(lvalue.extract(initSyncSignals));
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init_rvalue.append(lvalue.extract(initSyncSignals, &rvalue));
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lvalue.remove2(initSyncSignals, &rvalue);
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}
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assert(lvalue.width == rvalue.width);
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lvalue.optimize();
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rvalue.optimize();
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@ -56,8 +56,46 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
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if (!flag_nomem2reg && !get_bool_attribute("\\nomem2reg"))
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{
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std::set<AstNode*> mem2reg_set, mem2reg_candidates;
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mem2reg_as_needed_pass1(mem2reg_set, mem2reg_candidates, false, false, flag_mem2reg);
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std::map<AstNode*, std::set<std::string>> mem2reg_places;
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std::map<AstNode*, uint32_t> mem2reg_candidates, dummy_proc_flags;
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uint32_t flags = flag_mem2reg ? AstNode::MEM2REG_FL_ALL : 0;
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mem2reg_as_needed_pass1(mem2reg_places, mem2reg_candidates, dummy_proc_flags, flags);
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std::set<AstNode*> mem2reg_set;
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for (auto &it : mem2reg_candidates)
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{
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AstNode *mem = it.first;
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uint32_t memflags = it.second;
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assert((memflags & ~0x00ffff00) == 0);
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if (mem->get_bool_attribute("\\nomem2reg"))
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continue;
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if (memflags & AstNode::MEM2REG_FL_FORCED)
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goto silent_activate;
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if (memflags & AstNode::MEM2REG_FL_EQ2)
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goto verbose_activate;
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if ((memflags & AstNode::MEM2REG_FL_SET_INIT) && (memflags & AstNode::MEM2REG_FL_SET_ELSE))
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goto verbose_activate;
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continue;
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verbose_activate:
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if (mem2reg_set.count(mem) == 0) {
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log("Warning: Replacing memory %s with list of registers.", mem->str.c_str());
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bool first_element = true;
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for (auto &place : mem2reg_places[it.first]) {
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log("%s%s", first_element ? " See " : ", ", place.c_str());
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first_element = false;
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}
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log("\n");
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}
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silent_activate:
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mem2reg_set.insert(mem);
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}
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for (auto node : mem2reg_set)
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{
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@ -1249,36 +1287,102 @@ void AstNode::replace_ids(std::map<std::string, std::string> &rules)
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}
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// find memories that should be replaced by registers
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void AstNode::mem2reg_as_needed_pass1(std::set<AstNode*> &mem2reg_set, std::set<AstNode*> &mem2reg_candidates, bool sync_proc, bool async_proc, bool force_mem2reg)
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void AstNode::mem2reg_as_needed_pass1(std::map<AstNode*, std::set<std::string>> &mem2reg_places,
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std::map<AstNode*, uint32_t> &mem2reg_candidates, std::map<AstNode*, uint32_t> &proc_flags, uint32_t &flags)
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{
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if ((type == AST_ASSIGN_LE && async_proc) || (type == AST_ASSIGN_EQ && (sync_proc || async_proc)))
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if (children[0]->type == AST_IDENTIFIER && children[0]->id2ast && children[0]->id2ast->type == AST_MEMORY &&
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!children[0]->id2ast->get_bool_attribute("\\nomem2reg")) {
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if (async_proc || mem2reg_candidates.count(children[0]->id2ast) > 0) {
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if (mem2reg_set.count(children[0]->id2ast) == 0)
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log("Warning: Replacing memory %s with list of registers because of assignment in line %s:%d.\n",
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children[0]->str.c_str(), filename.c_str(), linenum);
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mem2reg_set.insert(children[0]->id2ast);
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uint32_t children_flags = 0;
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int ignore_children_counter = 0;
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if (type == AST_ASSIGN || type == AST_ASSIGN_LE || type == AST_ASSIGN_EQ)
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{
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if (children[0]->type == AST_IDENTIFIER && children[0]->id2ast && children[0]->id2ast->type == AST_MEMORY)
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{
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AstNode *mem = children[0]->id2ast;
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// activate mem2reg if this is assigned in an async proc
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if (flags & AstNode::MEM2REG_FL_ASYNC) {
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if (!(mem2reg_candidates[mem] & AstNode::MEM2REG_FL_SET_ASYNC))
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mem2reg_places[mem].insert(stringf("%s:%d", filename.c_str(), linenum));
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mem2reg_candidates[mem] |= AstNode::MEM2REG_FL_SET_ASYNC;
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}
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// remember if this is assigned blocking (=)
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if (type == AST_ASSIGN_EQ) {
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if (!(proc_flags[mem] & AstNode::MEM2REG_FL_EQ1))
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mem2reg_places[mem].insert(stringf("%s:%d", filename.c_str(), linenum));
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proc_flags[mem] |= AstNode::MEM2REG_FL_EQ1;
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}
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// remember where this is
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if (flags & MEM2REG_FL_INIT) {
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if (!(mem2reg_candidates[mem] & AstNode::MEM2REG_FL_SET_INIT))
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mem2reg_places[mem].insert(stringf("%s:%d", filename.c_str(), linenum));
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mem2reg_candidates[mem] |= AstNode::MEM2REG_FL_SET_INIT;
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} else {
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if (!(mem2reg_candidates[mem] & AstNode::MEM2REG_FL_SET_ELSE))
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mem2reg_places[mem].insert(stringf("%s:%d", filename.c_str(), linenum));
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mem2reg_candidates[mem] |= AstNode::MEM2REG_FL_SET_ELSE;
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}
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mem2reg_candidates.insert(children[0]->id2ast);
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}
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if (type == AST_MEMORY && (get_bool_attribute("\\mem2reg") || force_mem2reg))
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mem2reg_set.insert(this);
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ignore_children_counter = 1;
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}
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if (type == AST_IDENTIFIER && id2ast && id2ast->type == AST_MEMORY)
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{
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AstNode *mem = id2ast;
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// flag if used after blocking assignment (in same proc)
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if ((proc_flags[mem] & AstNode::MEM2REG_FL_EQ1) && !(mem2reg_candidates[mem] & AstNode::MEM2REG_FL_EQ2)) {
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mem2reg_places[mem].insert(stringf("%s:%d", filename.c_str(), linenum));
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mem2reg_candidates[mem] |= AstNode::MEM2REG_FL_EQ2;
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}
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}
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// also activate if requested, either by using mem2reg attribute or by declaring array as 'wire' instead of 'reg'
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if (type == AST_MEMORY && (get_bool_attribute("\\mem2reg") || (flags & AstNode::MEM2REG_FL_ALL) || !is_reg))
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mem2reg_candidates[this] |= AstNode::MEM2REG_FL_FORCED;
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if (type == AST_MODULE && get_bool_attribute("\\mem2reg"))
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force_mem2reg = true;
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children_flags |= AstNode::MEM2REG_FL_ALL;
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std::map<AstNode*, uint32_t> *proc_flags_p = NULL;
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if (type == AST_ALWAYS) {
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bool sync_proc = false;
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for (auto child : children) {
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if (child->type == AST_POSEDGE || child->type == AST_NEGEDGE)
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sync_proc = true;
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}
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async_proc = !sync_proc;
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if (!sync_proc)
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children_flags |= AstNode::MEM2REG_FL_ASYNC;
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proc_flags_p = new std::map<AstNode*, uint32_t>;
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}
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if (type == AST_INITIAL) {
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children_flags |= AstNode::MEM2REG_FL_INIT;
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proc_flags_p = new std::map<AstNode*, uint32_t>;
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}
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uint32_t backup_flags = flags;
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flags |= children_flags;
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assert((flags & ~0x000000ff) == 0);
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for (auto child : children)
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child->mem2reg_as_needed_pass1(mem2reg_set, mem2reg_candidates, sync_proc, async_proc, force_mem2reg);
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if (ignore_children_counter > 0)
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ignore_children_counter--;
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else if (proc_flags_p)
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child->mem2reg_as_needed_pass1(mem2reg_places, mem2reg_candidates, *proc_flags_p, flags);
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else
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child->mem2reg_as_needed_pass1(mem2reg_places, mem2reg_candidates, proc_flags, flags);
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flags &= ~children_flags | backup_flags;
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if (proc_flags_p) {
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for (auto it : *proc_flags_p)
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assert((it.second & ~0xff000000) == 0);
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delete proc_flags_p;
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}
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}
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// actually replace memories with registers
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@ -1287,8 +1391,8 @@ void AstNode::mem2reg_as_needed_pass2(std::set<AstNode*> &mem2reg_set, AstNode *
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if (type == AST_BLOCK)
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block = this;
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if ((type == AST_ASSIGN_LE || type == AST_ASSIGN_EQ) && block != NULL &&
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children[0]->id2ast && mem2reg_set.count(children[0]->id2ast) > 0)
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if ((type == AST_ASSIGN_LE || type == AST_ASSIGN_EQ) && block != NULL && children[0]->id2ast &&
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mem2reg_set.count(children[0]->id2ast) > 0 && children[0]->children[0]->children[0]->type != AST_CONSTANT)
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{
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std::stringstream sstr;
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sstr << "$mem2reg_wr$" << children[0]->str << "$" << filename << ":" << linenum << "$" << (RTLIL::autoidx++);
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@ -1344,77 +1448,89 @@ void AstNode::mem2reg_as_needed_pass2(std::set<AstNode*> &mem2reg_set, AstNode *
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if (type == AST_IDENTIFIER && id2ast && mem2reg_set.count(id2ast) > 0)
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{
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std::stringstream sstr;
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sstr << "$mem2reg_rd$" << children[0]->str << "$" << filename << ":" << linenum << "$" << (RTLIL::autoidx++);
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std::string id_addr = sstr.str() + "_ADDR", id_data = sstr.str() + "_DATA";
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int mem_width, mem_size, addr_bits;
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id2ast->meminfo(mem_width, mem_size, addr_bits);
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AstNode *wire_addr = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(addr_bits-1, true), mkconst_int(0, true)));
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wire_addr->str = id_addr;
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wire_addr->is_reg = true;
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if (block)
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wire_addr->attributes["\\nosync"] = AstNode::mkconst_int(1, false);
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mod->children.push_back(wire_addr);
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while (wire_addr->simplify(true, false, false, 1, -1, false)) { }
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AstNode *wire_data = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(mem_width-1, true), mkconst_int(0, true)));
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wire_data->str = id_data;
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wire_data->is_reg = true;
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if (block)
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wire_data->attributes["\\nosync"] = AstNode::mkconst_int(1, false);
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mod->children.push_back(wire_data);
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while (wire_data->simplify(true, false, false, 1, -1, false)) { }
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AstNode *assign_addr = new AstNode(block ? AST_ASSIGN_EQ : AST_ASSIGN, new AstNode(AST_IDENTIFIER), children[0]->children[0]->clone());
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assign_addr->children[0]->str = id_addr;
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AstNode *case_node = new AstNode(AST_CASE, new AstNode(AST_IDENTIFIER));
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case_node->children[0]->str = id_addr;
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for (int i = 0; i < mem_size; i++) {
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if (children[0]->children[0]->type == AST_CONSTANT && int(children[0]->children[0]->integer) != i)
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continue;
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AstNode *cond_node = new AstNode(AST_COND, AstNode::mkconst_int(i, false, addr_bits), new AstNode(AST_BLOCK));
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AstNode *assign_reg = new AstNode(AST_ASSIGN_EQ, new AstNode(AST_IDENTIFIER), new AstNode(AST_IDENTIFIER));
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assign_reg->children[0]->str = id_data;
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assign_reg->children[1]->str = stringf("%s[%d]", str.c_str(), i);
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cond_node->children[1]->children.push_back(assign_reg);
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case_node->children.push_back(cond_node);
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}
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std::vector<RTLIL::State> x_bits;
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for (int i = 0; i < mem_width; i++)
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x_bits.push_back(RTLIL::State::Sx);
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AstNode *cond_node = new AstNode(AST_COND, new AstNode(AST_DEFAULT), new AstNode(AST_BLOCK));
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AstNode *assign_reg = new AstNode(AST_ASSIGN_EQ, new AstNode(AST_IDENTIFIER), AstNode::mkconst_bits(x_bits, false));
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assign_reg->children[0]->str = id_data;
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cond_node->children[1]->children.push_back(assign_reg);
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case_node->children.push_back(cond_node);
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if (block)
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if (children[0]->children[0]->type == AST_CONSTANT)
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{
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size_t assign_idx = 0;
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while (assign_idx < block->children.size() && !block->children[assign_idx]->contains(this))
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assign_idx++;
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assert(assign_idx < block->children.size());
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block->children.insert(block->children.begin()+assign_idx, case_node);
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block->children.insert(block->children.begin()+assign_idx, assign_addr);
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int id = children[0]->children[0]->integer;
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str = stringf("%s[%d]", str.c_str(), id);
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delete_children();
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range_valid = false;
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id2ast = NULL;
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}
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else
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{
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AstNode *proc = new AstNode(AST_ALWAYS, new AstNode(AST_BLOCK));
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proc->children[0]->children.push_back(case_node);
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mod->children.push_back(proc);
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mod->children.push_back(assign_addr);
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}
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std::stringstream sstr;
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sstr << "$mem2reg_rd$" << children[0]->str << "$" << filename << ":" << linenum << "$" << (RTLIL::autoidx++);
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std::string id_addr = sstr.str() + "_ADDR", id_data = sstr.str() + "_DATA";
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delete_children();
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range_valid = false;
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id2ast = NULL;
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str = id_data;
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int mem_width, mem_size, addr_bits;
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id2ast->meminfo(mem_width, mem_size, addr_bits);
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AstNode *wire_addr = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(addr_bits-1, true), mkconst_int(0, true)));
|
||||
wire_addr->str = id_addr;
|
||||
wire_addr->is_reg = true;
|
||||
if (block)
|
||||
wire_addr->attributes["\\nosync"] = AstNode::mkconst_int(1, false);
|
||||
mod->children.push_back(wire_addr);
|
||||
while (wire_addr->simplify(true, false, false, 1, -1, false)) { }
|
||||
|
||||
AstNode *wire_data = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(mem_width-1, true), mkconst_int(0, true)));
|
||||
wire_data->str = id_data;
|
||||
wire_data->is_reg = true;
|
||||
if (block)
|
||||
wire_data->attributes["\\nosync"] = AstNode::mkconst_int(1, false);
|
||||
mod->children.push_back(wire_data);
|
||||
while (wire_data->simplify(true, false, false, 1, -1, false)) { }
|
||||
|
||||
AstNode *assign_addr = new AstNode(block ? AST_ASSIGN_EQ : AST_ASSIGN, new AstNode(AST_IDENTIFIER), children[0]->children[0]->clone());
|
||||
assign_addr->children[0]->str = id_addr;
|
||||
|
||||
AstNode *case_node = new AstNode(AST_CASE, new AstNode(AST_IDENTIFIER));
|
||||
case_node->children[0]->str = id_addr;
|
||||
|
||||
for (int i = 0; i < mem_size; i++) {
|
||||
if (children[0]->children[0]->type == AST_CONSTANT && int(children[0]->children[0]->integer) != i)
|
||||
continue;
|
||||
AstNode *cond_node = new AstNode(AST_COND, AstNode::mkconst_int(i, false, addr_bits), new AstNode(AST_BLOCK));
|
||||
AstNode *assign_reg = new AstNode(AST_ASSIGN_EQ, new AstNode(AST_IDENTIFIER), new AstNode(AST_IDENTIFIER));
|
||||
assign_reg->children[0]->str = id_data;
|
||||
assign_reg->children[1]->str = stringf("%s[%d]", str.c_str(), i);
|
||||
cond_node->children[1]->children.push_back(assign_reg);
|
||||
case_node->children.push_back(cond_node);
|
||||
}
|
||||
|
||||
std::vector<RTLIL::State> x_bits;
|
||||
for (int i = 0; i < mem_width; i++)
|
||||
x_bits.push_back(RTLIL::State::Sx);
|
||||
|
||||
AstNode *cond_node = new AstNode(AST_COND, new AstNode(AST_DEFAULT), new AstNode(AST_BLOCK));
|
||||
AstNode *assign_reg = new AstNode(AST_ASSIGN_EQ, new AstNode(AST_IDENTIFIER), AstNode::mkconst_bits(x_bits, false));
|
||||
assign_reg->children[0]->str = id_data;
|
||||
cond_node->children[1]->children.push_back(assign_reg);
|
||||
case_node->children.push_back(cond_node);
|
||||
|
||||
if (block)
|
||||
{
|
||||
size_t assign_idx = 0;
|
||||
while (assign_idx < block->children.size() && !block->children[assign_idx]->contains(this))
|
||||
assign_idx++;
|
||||
assert(assign_idx < block->children.size());
|
||||
block->children.insert(block->children.begin()+assign_idx, case_node);
|
||||
block->children.insert(block->children.begin()+assign_idx, assign_addr);
|
||||
}
|
||||
else
|
||||
{
|
||||
AstNode *proc = new AstNode(AST_ALWAYS, new AstNode(AST_BLOCK));
|
||||
proc->children[0]->children.push_back(case_node);
|
||||
mod->children.push_back(proc);
|
||||
mod->children.push_back(assign_addr);
|
||||
}
|
||||
|
||||
delete_children();
|
||||
range_valid = false;
|
||||
id2ast = NULL;
|
||||
str = id_data;
|
||||
}
|
||||
}
|
||||
|
||||
assert(id2ast == NULL || mem2reg_set.count(id2ast) == 0);
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue