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Move rename logic to abc_ops_reintegrate

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Lofty 2026-06-10 10:01:25 +01:00
parent c96d7bc998
commit 091d2a7814
11 changed files with 208 additions and 281 deletions
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tests/arch/quicklogic/pp3/logic.ys
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@ -5,8 +5,8 @@ equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cel
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 1 t:LUT1
select -assert-count 6 t:LUT2
select -assert-count 4 t:LUT1
select -assert-count 3 t:LUT2
select -assert-count 2 t:LUT3
select -assert-count 8 t:inpad
select -assert-count 10 t:outpad