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Move rename logic to abc_ops_reintegrate

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Lofty 2026-06-10 10:01:25 +01:00
parent c96d7bc998
commit 091d2a7814
11 changed files with 208 additions and 281 deletions
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36
tests/aiger/neg.ys
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@ -1,36 +0,0 @@
read_verilog <<EOT
module top(input [31:-32] a, input [-65:-128] b, output [128:65] c);
assign c = a & b;
endmodule
EOT
select -assert-count 1 i:a
select -assert-count 1 i:b
select -assert-count 1 o:c
select -assert-count 3 x:* s:64 %i
design -save read
!rm -rf neg.out
!mkdir neg.out
simplemap
write_aiger -map neg.out/neg.map neg.out/neg.aig
design -reset
read_aiger -wideports -map neg.out/neg.map neg.out/neg.aig
select -assert-count 1 i:a
select -assert-count 1 i:b
select -assert-count 1 o:c
select -assert-count 3 x:* s:64 %i
design -load read
!rm -rf neg.out
!mkdir neg.out
simplemap
write_xaiger -map neg.out/neg.map neg.out/neg.aig
design -reset
read_aiger -wideports -map neg.out/neg.map neg.out/neg.aig
select -assert-count 1 i:a
select -assert-count 1 i:b
select -assert-count 1 o:c
select -assert-count 3 x:* s:64 %i