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Move rename logic to abc_ops_reintegrate

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This commit is contained in:
Lofty 2026-06-10 10:01:25 +01:00
parent c96d7bc998
commit 091d2a7814
11 changed files with 208 additions and 281 deletions
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8
passes/techmap/abc9.cc
View file

@ -377,8 +377,8 @@ struct Abc9Pass : public ScriptPass
run(" abc9_ops -write_box <abc-temp-dir>/input.box", "(skip if '-box')");
run(" write_xaiger -map <abc-temp-dir>/input.sym [-dff] <abc-temp-dir>/input.xaig");
run(" abc9_exe [options] -cwd <abc-temp-dir> -lut [<abc-temp-dir>/input.lut] -box [<abc-temp-dir>/input.box]");
run(" read_aiger -xaiger -wideports -module_name <module-name>$abc9 -map <abc-temp-dir>/input.sym <abc-temp-dir>/output.aig");
run(" abc_ops_reintegrate [-dff]");
run(" read_aiger -xaiger -module_name <module-name>$abc9 <abc-temp-dir>/output.aig");
run(" abc_ops_reintegrate -map <abc-temp-dir>/input.sym [-dff]");
}
else {
auto selected_modules = active_design->selected_modules();
@ -429,8 +429,8 @@ struct Abc9Pass : public ScriptPass
else
abc9_exe_cmd += stringf(" -box %s", box_file);
run_nocheck(abc9_exe_cmd);
run_nocheck(stringf("read_aiger -xaiger -wideports -module_name %s$abc9 -map %s/input.sym %s/output.aig", mod, tempdir_name, tempdir_name));
run_nocheck(stringf("abc_ops_reintegrate %s", dff_mode ? "-dff" : ""));
run_nocheck(stringf("read_aiger -xaiger -module_name %s$abc9 %s/output.aig", mod, tempdir_name));
run_nocheck(stringf("abc_ops_reintegrate -map %s/input.sym %s", tempdir_name, dff_mode ? "-dff" : ""));
}
else
log("Don't call ABC as there is nothing to map.\n");

177
passes/techmap/abc_ops_reintegrate.cc
View file

@ -34,7 +34,7 @@ inline std::string remap_name(RTLIL::IdString abc9_name)
return stringf("$abc$%d$%s", map_autoidx, abc9_name.c_str()+1);
}
void reintegrate(RTLIL::Module *module, bool dff_mode)
void reintegrate(RTLIL::Module *module, bool dff_mode, std::string map_filename)
{
auto design = module->design;
log_assert(design);
@ -45,6 +45,167 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
if (mapped_mod == NULL)
log_error("ABC output file does not contain a module `%s$abc'.\n", module);
int input_count = design->scratchpad_get_int("read_aiger.inputs", 0);
int output_count = design->scratchpad_get_int("read_aiger.outputs", 0);
int co_count = design->scratchpad_get_int("read_aiger.co_count", 0);
dict<RTLIL::IdString, std::pair<int,int>> wideports_cache;
if (!map_filename.empty()) {
std::ifstream mf(map_filename);
std::string type, symbol;
int variable, index;
while (mf >> type >> variable >> index >> symbol) {
RTLIL::IdString escaped_s = RTLIL::escape_id(symbol);
if (type == "input") {
log_assert(variable < input_count);
RTLIL::Wire* wire = mapped_mod->wire(stringf("$aiger$i%d", variable + 1));
log_assert(wire);
log_assert(wire->port_input);
log_debug("Renaming input %s", wire);
RTLIL::Wire *existing = nullptr;
if (index == 0) {
// Cope with the fact that a CI might be identical
// to a PI (necessary due to ABC); in those cases
// simply connect the latter to the former
existing = mapped_mod->wire(escaped_s);
if (!existing)
mapped_mod->rename(wire, escaped_s);
else {
wire->port_input = false;
mapped_mod->connect(wire, existing);
}
log_debug(" -> %s\n", escaped_s);
}
else {
RTLIL::IdString indexed_name = stringf("%s[%d]", escaped_s, index);
existing = mapped_mod->wire(indexed_name);
if (!existing)
mapped_mod->rename(wire, indexed_name);
else {
mapped_mod->connect(wire, existing);
wire->port_input = false;
}
log_debug(" -> %s\n", indexed_name);
}
if (!existing) {
auto r = wideports_cache.insert(escaped_s);
if (r.second) {
r.first->second.first = index;
r.first->second.second = index;
}
else {
r.first->second.first = std::min(r.first->second.first, index);
r.first->second.second = std::max(r.first->second.second, index);
}
}
}
else if (type == "output") {
log_assert(variable + co_count < output_count);
RTLIL::Wire* wire = mapped_mod->wire(stringf("$aiger$o%d", variable + co_count));
log_assert(wire);
log_assert(wire->port_output);
log_debug("Renaming output %s", wire);
RTLIL::Wire *existing;
if (index == 0) {
// Cope with the fact that a CO might be identical
// to a PO (necessary due to ABC); in those cases
// simply connect the latter to the former
existing = mapped_mod->wire(escaped_s);
if (!existing)
mapped_mod->rename(wire, escaped_s);
else {
wire->port_output = false;
existing->port_output = true;
mapped_mod->connect(wire, existing);
wire = existing;
}
log_debug(" -> %s\n", escaped_s);
}
else {
RTLIL::IdString indexed_name = stringf("%s[%d]", escaped_s, index);
existing = mapped_mod->wire(indexed_name);
if (!existing)
mapped_mod->rename(wire, indexed_name);
else {
wire->port_output = false;
existing->port_output = true;
mapped_mod->connect(wire, existing);
}
log_debug(" -> %s\n", indexed_name);
}
if (!existing) {
auto r = wideports_cache.insert(escaped_s);
if (r.second) {
r.first->second.first = index;
r.first->second.second = index;
}
else {
r.first->second.first = std::min(r.first->second.first, index);
r.first->second.second = std::max(r.first->second.second, index);
}
}
}
else if (type == "box") {
RTLIL::Cell* cell = mapped_mod->cell(stringf("$box%d", variable));
if (!cell)
log_debug("Box %d (%s) no longer exists.\n", variable, escaped_s.unescape());
else
mapped_mod->rename(cell, escaped_s);
}
else
log_error("Symbol type '%s' not recognised.\n", type);
}
}
for (auto &wp : wideports_cache) {
auto name = wp.first;
int min = wp.second.first;
int max = wp.second.second;
if (min == 0 && max == 0)
continue;
RTLIL::Wire *wire = mapped_mod->wire(name);
if (wire)
mapped_mod->rename(wire, RTLIL::escape_id(stringf("%s[%d]", name, 0)));
// Do not make ports with a mix of input/output into
// wide ports
bool port_input = false, port_output = false;
for (int i = min; i <= max; i++) {
RTLIL::IdString other_name = name.str() + stringf("[%d]", i);
RTLIL::Wire *other_wire = mapped_mod->wire(other_name);
if (other_wire) {
port_input = port_input || other_wire->port_input;
port_output = port_output || other_wire->port_output;
}
}
wire = mapped_mod->addWire(name, max-min+1);
wire->start_offset = min;
wire->port_input = port_input;
wire->port_output = port_output;
for (int i = min; i <= max; i++) {
RTLIL::IdString other_name = stringf("%s[%d]", name, i);
RTLIL::Wire *other_wire = mapped_mod->wire(other_name);
if (other_wire) {
other_wire->port_input = false;
other_wire->port_output = false;
if (wire->port_input)
mapped_mod->connect(other_wire, SigSpec(wire, i-min));
else
mapped_mod->connect(SigSpec(wire, i-min), other_wire);
}
}
}
mapped_mod->fixup_ports();
for (auto w : mapped_mod->wires()) {
auto nw = module->addWire(remap_name(w->name), GetSize(w));
nw->start_offset = w->start_offset;
@ -475,12 +636,20 @@ struct AbcOpsReintegratePass : public Pass {
log("by first recovering ABC9 boxes, and then stitching in the remaining\n");
log("primary inputs and outputs.\n");
log("\n");
log(" -dff\n");
log(" consider flop cells (those instantiating modules marked with\n");
log(" (* abc9_flop *)) during -prep_{delays,xaiger,box}.\n");
log("\n");
log(" -map <filename>\n");
log(" read file with port and latch symbols\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing ABC_OPS_REINTEGRATE pass (reintegrate ABC mapped design into module).\n");
bool dff_mode = false;
std::string map_filename;
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {
@ -489,6 +658,10 @@ struct AbcOpsReintegratePass : public Pass {
dff_mode = true;
continue;
}
if (map_filename.empty() && arg == "-map" && argidx+1 < args.size()) {
map_filename = args[++argidx];
continue;
}
}
extra_args(args, argidx, design);
@ -501,7 +674,7 @@ struct AbcOpsReintegratePass : public Pass {
if (!design->selected_whole_module(mod))
log_error("Can't handle partially selected module %s!\n", mod);
reintegrate(mod, dff_mode);
reintegrate(mod, dff_mode, map_filename);
}
}
} AbcOpsReintegratePass;