3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-07-02 05:26:07 +00:00

Move rename logic to abc_ops_reintegrate

This commit is contained in:
Lofty 2026-06-10 10:01:25 +01:00
parent c96d7bc998
commit 091d2a7814
11 changed files with 208 additions and 281 deletions

View file

@ -32,7 +32,6 @@ struct AigerReader
RTLIL::IdString clk_name;
RTLIL::Module *module;
std::string map_filename;
bool wideports;
const int aiger_autoidx;
unsigned M, I, L, O, A;
@ -47,7 +46,7 @@ struct AigerReader
std::vector<RTLIL::Cell*> boxes;
std::vector<int> mergeability, initial_state;
AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name, std::string map_filename, bool wideports);
AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name, std::string map_filename);
void parse_aiger();
void parse_xaiger();
void parse_aiger_ascii();