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Remove sequential extension

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This commit is contained in:
Eddie Hung 2019-08-20 18:16:37 -07:00
parent bbab608691
commit 091bf4a18b
9 changed files with 68 additions and 730 deletions
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119
techlibs/xilinx/abc_unmap.v
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@ -20,125 +20,6 @@
// ============================================================================
module \$__ABC_ASYNC (input A, S, output Y);
assign Y = A;
endmodule
module \$__ABC_FDRE (output Q,
input C,
input CE,
input D,
input R, \$pastQ );
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_R_INVERTED = 1'b0;
parameter CLK_POLARITY = !IS_C_INVERTED;
parameter EN_POLARITY = 1'b1;
FDRE #(
.INIT(INIT),
.IS_C_INVERTED(IS_C_INVERTED),
.IS_D_INVERTED(IS_D_INVERTED),
.IS_R_INVERTED(IS_R_INVERTED),
) _TECHMAP_REPLACE_ (
.D(D), .Q(Q), .C(C), .CE(CE), .R(R)
);
endmodule
module \$__ABC_FDRE_1 (output Q,
input C,
input CE,
input D,
input R, \$pastQ );
parameter [0:0] INIT = 1'b0;
parameter CLK_POLARITY = 1'b0;
parameter EN_POLARITY = 1'b1;
assign Q = R ? 1'b0 : (CE ? D : \$pastQ );
FDRE_1 #(
.INIT(INIT),
) _TECHMAP_REPLACE_ (
.D(D), .Q(Q), .C(C), .CE(CE), .R(R)
);
endmodule
module \$__ABC_FDCE (output Q,
input C,
input CE,
input D,
input CLR, \$pastQ );
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_CLR_INVERTED = 1'b0;
parameter CLK_POLARITY = !IS_C_INVERTED;
parameter EN_POLARITY = 1'b1;
FDCE #(
.INIT(INIT),
.IS_C_INVERTED(IS_C_INVERTED),
.IS_D_INVERTED(IS_D_INVERTED),
.IS_CLR_INVERTED(IS_CLR_INVERTED),
) _TECHMAP_REPLACE_ (
.D(D), .Q(Q), .C(C), .CE(CE), .CLR(CLR)
);
endmodule
module \$__ABC_FDCE_1 (output Q,
input C,
input CE,
input D,
input CLR, \$pastQ );
parameter [0:0] INIT = 1'b0;
parameter CLK_POLARITY = 1'b0;
parameter EN_POLARITY = 1'b1;
FDCE_1 #(
.INIT(INIT),
) _TECHMAP_REPLACE_ (
.D(D), .Q(Q), .C(C), .CE(CE), .CLR(CLR)
);
endmodule
module \$__ABC_FDPE (output Q,
input C,
input CE,
input D,
input PRE, \$pastQ );
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_PRE_INVERTED = 1'b0;
parameter CLK_POLARITY = !IS_C_INVERTED;
parameter EN_POLARITY = 1'b1;
FDPE #(
.INIT(INIT),
.IS_C_INVERTED(IS_C_INVERTED),
.IS_D_INVERTED(IS_D_INVERTED),
.IS_PRE_INVERTED(IS_PRE_INVERTED),
) _TECHMAP_REPLACE_ (
.D(D), .Q(Q), .C(C), .CE(CE), .PRE(PRE)
);
endmodule
module \$__ABC_FDPE_1 (output Q,
input C,
input CE,
input D,
input PRE, \$pastQ );
parameter [0:0] INIT = 1'b0;
parameter CLK_POLARITY = 1'b0;
parameter EN_POLARITY = 1'b1;
FDPE_1 #(
.INIT(INIT),
) _TECHMAP_REPLACE_ (
.D(D), .Q(Q), .C(C), .CE(CE), .PRE(PRE)
);
endmodule
module \$__ABC_LUTMUX6 (input A, input [5:0] S, output Y);
assign Y = A;
endmodule