mirror of
https://github.com/YosysHQ/yosys
synced 2026-04-06 12:44:52 +00:00
Fix test cases.
This commit is contained in:
nella
parent
e4cb560163
commit
0909e462c3
6 changed files with 67 additions and 195 deletions
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@ -213,8 +213,7 @@ struct Rewriter {
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return false;
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}
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std::vector<Operand> extract_chain_operands(const pool<Cell *> &chain, Cell *root, const dict<Cell *, Cell *> &parent_of,
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int &neg_compensation)
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std::vector<Operand> extract_chain_operands(const pool<Cell *> &chain, Cell *root, const dict<Cell *, Cell *> &parent_of, int &neg_compensation)
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{
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pool<SigBit> chain_bits = internal_bits(chain);
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@ -60,18 +60,22 @@ select -assert-count 14 t:$fa
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select -assert-count 1 t:$add
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design -reset
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read_verilog <<EOT
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read_verilog -icells <<EOT
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module alu_add3(
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input [7:0] a, b, c,
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output [7:0] y
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);
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assign y = a + b + c;
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wire [7:0] tmp, x1, x2, co1, co2;
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// a + b
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$alu #(.A_WIDTH(8), .B_WIDTH(8), .Y_WIDTH(8), .A_SIGNED(0), .B_SIGNED(0))
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alu1 (.A(a), .B(b), .BI(1'b0), .CI(1'b0), .Y(tmp), .X(x1), .CO(co1));
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// tmp + c
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$alu #(.A_WIDTH(8), .B_WIDTH(8), .Y_WIDTH(8), .A_SIGNED(0), .B_SIGNED(0))
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alu2 (.A(tmp), .B(c), .BI(1'b0), .CI(1'b0), .Y(y), .X(x2), .CO(co2));
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endmodule
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EOT
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hierarchy -auto-top
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proc
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alumacc
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opt_clean
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select -assert-count 2 t:$alu
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csa_tree
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opt_clean
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select -assert-count 1 t:$fa
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@ -79,18 +83,25 @@ select -assert-count 1 t:$add
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select -assert-none t:$alu
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design -reset
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read_verilog <<EOT
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read_verilog -icells <<EOT
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module alu_add4(
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input [7:0] a, b, c, d,
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output [7:0] y
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);
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assign y = a + b + c + d;
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wire [7:0] tmp1, tmp2, x1, x2, x3, co1, co2, co3;
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// a + b
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$alu #(.A_WIDTH(8), .B_WIDTH(8), .Y_WIDTH(8), .A_SIGNED(0), .B_SIGNED(0))
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alu1 (.A(a), .B(b), .BI(1'b0), .CI(1'b0), .Y(tmp1), .X(x1), .CO(co1));
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// c + d
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$alu #(.A_WIDTH(8), .B_WIDTH(8), .Y_WIDTH(8), .A_SIGNED(0), .B_SIGNED(0))
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alu2 (.A(c), .B(d), .BI(1'b0), .CI(1'b0), .Y(tmp2), .X(x2), .CO(co2));
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// tmp1 + tmp2
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$alu #(.A_WIDTH(8), .B_WIDTH(8), .Y_WIDTH(8), .A_SIGNED(0), .B_SIGNED(0))
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alu3 (.A(tmp1), .B(tmp2), .BI(1'b0), .CI(1'b0), .Y(y), .X(x3), .CO(co3));
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endmodule
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EOT
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hierarchy -auto-top
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proc
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alumacc
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opt_clean
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select -assert-count 3 t:$alu
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csa_tree
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opt_clean
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select -assert-count 2 t:$fa
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@ -98,18 +109,28 @@ select -assert-count 1 t:$add
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select -assert-none t:$alu
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design -reset
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read_verilog <<EOT
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read_verilog -icells <<EOT
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module alu_add5(
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input [11:0] a, b, c, d, e,
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output [11:0] y
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);
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assign y = a + b + c + d + e;
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wire [11:0] tmp1, tmp2, tmp3, x1, x2, x3, x4, co1, co2, co3, co4;
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// a + b
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$alu #(.A_WIDTH(12), .B_WIDTH(12), .Y_WIDTH(12), .A_SIGNED(0), .B_SIGNED(0))
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alu1 (.A(a), .B(b), .BI(1'b0), .CI(1'b0), .Y(tmp1), .X(x1), .CO(co1));
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// c + d
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$alu #(.A_WIDTH(12), .B_WIDTH(12), .Y_WIDTH(12), .A_SIGNED(0), .B_SIGNED(0))
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alu2 (.A(c), .B(d), .BI(1'b0), .CI(1'b0), .Y(tmp2), .X(x2), .CO(co2));
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// tmp1 + tmp2
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$alu #(.A_WIDTH(12), .B_WIDTH(12), .Y_WIDTH(12), .A_SIGNED(0), .B_SIGNED(0))
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alu3 (.A(tmp1), .B(tmp2), .BI(1'b0), .CI(1'b0), .Y(tmp3), .X(x3), .CO(co3));
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// tmp3 + e
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$alu #(.A_WIDTH(12), .B_WIDTH(12), .Y_WIDTH(12), .A_SIGNED(0), .B_SIGNED(0))
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alu4 (.A(tmp3), .B(e), .BI(1'b0), .CI(1'b0), .Y(y), .X(x4), .CO(co4));
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endmodule
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EOT
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hierarchy -auto-top
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proc
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alumacc
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opt_clean
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select -assert-count 4 t:$alu
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csa_tree
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opt_clean
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select -assert-count 3 t:$fa
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@ -117,46 +138,7 @@ select -assert-count 1 t:$add
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select -assert-none t:$alu
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design -reset
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read_verilog <<EOT
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module alu_add8(
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input [15:0] a, b, c, d, e, f, g, h,
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output [15:0] y
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);
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assign y = a + b + c + d + e + f + g + h;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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alumacc
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opt_clean
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csa_tree
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opt_clean
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select -assert-count 6 t:$fa
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select -assert-count 1 t:$add
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select -assert-none t:$alu
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design -reset
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read_verilog <<EOT
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module alu_add16(
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input [15:0] a0, a1, a2, a3, a4, a5, a6, a7,
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input [15:0] a8, a9, a10, a11, a12, a13, a14, a15,
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output [15:0] y
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);
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assign y = a0 + a1 + a2 + a3 + a4 + a5 + a6 + a7
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+ a8 + a9 + a10 + a11 + a12 + a13 + a14 + a15;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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alumacc
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opt_clean
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csa_tree
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opt_clean
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select -assert-count 14 t:$fa
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select -assert-count 1 t:$add
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select -assert-none t:$alu
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design -reset
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# Test $macc cells (alumacc+opt output)
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read_verilog <<EOT
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module macc_add3(
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input [7:0] a, b, c,
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@ -176,25 +158,6 @@ select -assert-count 1 t:$add
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select -assert-none t:$macc t:$macc_v2 %u
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design -reset
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read_verilog <<EOT
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module macc_add4(
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input [7:0] a, b, c, d,
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output [7:0] y
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);
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assign y = a + b + c + d;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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alumacc
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opt
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csa_tree
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opt_clean
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select -assert-count 2 t:$fa
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select -assert-count 1 t:$add
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select -assert-none t:$macc t:$macc_v2 %u
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design -reset
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read_verilog <<EOT
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module macc_add5(
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input [11:0] a, b, c, d, e,
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@ -1,111 +1,3 @@
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read_verilog <<EOT
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module equiv_alu_add3(
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input [3:0] a, b, c,
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output [3:0] y
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);
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assign y = a + b + c;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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alumacc
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opt_clean
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equiv_opt csa_tree
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design -load postopt
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select -assert-count 1 t:$fa
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select -assert-count 1 t:$add
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design -reset
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read_verilog <<EOT
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module equiv_alu_add4(
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input [3:0] a, b, c, d,
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output [3:0] y
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);
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assign y = a + b + c + d;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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alumacc
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opt_clean
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equiv_opt csa_tree
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design -load postopt
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select -assert-count 2 t:$fa
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select -assert-count 1 t:$add
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design -reset
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read_verilog <<EOT
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module equiv_alu_add8(
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input [3:0] a, b, c, d, e, f, g, h,
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output [3:0] y
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);
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assign y = a + b + c + d + e + f + g + h;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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alumacc
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opt_clean
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equiv_opt csa_tree
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design -load postopt
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select -assert-count 6 t:$fa
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select -assert-count 1 t:$add
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design -reset
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read_verilog <<EOT
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module equiv_alu_signed(
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input signed [3:0] a, b, c, d,
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output signed [5:0] y
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);
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assign y = a + b + c + d;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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alumacc
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opt_clean
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equiv_opt csa_tree
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design -load postopt
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select -assert-count 2 t:$fa
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select -assert-count 1 t:$add
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design -reset
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read_verilog <<EOT
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module equiv_alu_sub_mixed(
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input [3:0] a, b, c, d,
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output [3:0] y
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);
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assign y = a + b - c + d;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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alumacc
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opt_clean
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equiv_opt csa_tree
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design -load postopt
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select -assert-min 1 t:$fa
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select -assert-count 1 t:$add
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design -reset
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read_verilog <<EOT
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module equiv_alu_sub_all(
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input [3:0] a, b, c, d,
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output [3:0] y
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);
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assign y = a - b - c - d;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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alumacc
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opt_clean
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equiv_opt csa_tree
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design -load postopt
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select -assert-min 1 t:$fa
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select -assert-count 1 t:$add
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design -reset
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read_verilog <<EOT
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module equiv_macc_add3(
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input [3:0] a, b, c,
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@ -195,3 +87,21 @@ design -load postopt
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select -assert-min 1 t:$fa
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select -assert-count 1 t:$add
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design -reset
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read_verilog <<EOT
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module equiv_macc_sub_all(
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input [3:0] a, b, c, d,
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output [3:0] y
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);
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assign y = a - b - c - d;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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alumacc
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opt
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equiv_opt csa_tree
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design -load postopt
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select -assert-min 1 t:$fa
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select -assert-count 1 t:$add
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design -reset
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@ -259,7 +259,7 @@ select -assert-none t:$fa
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design -reset
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read_verilog <<EOT
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module alu_mixed_width(
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module macc_mixed_width(
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input [7:0] a,
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input [3:0] b,
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input [15:0] c,
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@ -282,7 +282,7 @@ select -assert-none t:$sub
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design -reset
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read_verilog <<EOT
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module alu_signed(
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module macc_signed(
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input signed [7:0] a, b, c, d,
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output signed [9:0] y
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);
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@ -302,7 +302,7 @@ select -assert-none t:$sub
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design -reset
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read_verilog <<EOT
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module fir_4tap_alu(
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module fir_4tap_macc(
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input clk,
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input [15:0] x, c0, c1, c2, c3,
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output reg [31:0] y
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@ -328,7 +328,7 @@ select -assert-min 1 t:$dff
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design -reset
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read_verilog <<EOT
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module alu_mixed_sign(
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module macc_mixed_sign(
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input signed [7:0] a,
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input [7:0] b,
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input signed [7:0] c,
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@ -350,7 +350,7 @@ select -assert-none t:$sub
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design -reset
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read_verilog <<EOT
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module alu_wide32(
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module macc_wide32(
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input [31:0] a, b, c, d,
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output [31:0] y
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);
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@ -370,7 +370,7 @@ select -assert-none t:$sub
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design -reset
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read_verilog <<EOT
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module alu_single(
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module passthrough(
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input [7:0] a,
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output [7:0] y
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);
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@ -20,7 +20,7 @@ select -assert-none t:$sub
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design -reset
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read_verilog <<EOT
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module alu_idempotent(
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module macc_idempotent(
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input [15:0] a, b, c, d, e, f, g, h,
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output [15:0] y
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);
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@ -102,7 +102,7 @@ select -assert-none t:$sub
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design -reset
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read_verilog <<EOT
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module alu_sub_3op(
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module macc_sub_3op(
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input [7:0] a, b, c,
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output [7:0] y
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);
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@ -122,7 +122,7 @@ select -assert-none t:$sub
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design -reset
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read_verilog <<EOT
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module alu_sub_mixed(
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module macc_sub_mixed2(
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input [7:0] a, b, c, d,
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output [7:0] y
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);
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@ -142,7 +142,7 @@ select -assert-none t:$sub
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design -reset
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read_verilog <<EOT
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module alu_sub_all(
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module macc_sub_all(
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input [7:0] a, b, c, d,
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output [7:0] y
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);
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@ -162,7 +162,7 @@ select -assert-none t:$sub
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design -reset
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read_verilog <<EOT
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module alu_sub_signed(
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module macc_sub_signed(
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input signed [7:0] a, b, c, d,
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output signed [9:0] y
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);
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