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Renamed "sat_solve" pass to "sat"

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Clifford Wolf 2013-06-09 21:55:53 +02:00
parent a75b249427
commit 08e2fa978c
3 changed files with 12 additions and 12 deletions
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14
passes/sat/example.ys
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@ -2,12 +2,12 @@
read_verilog example.v
proc; opt_clean
sat_solve -set y 1'b1 example001
sat_solve -set y 1'b1 example002
sat_solve -set y_sshl 8'hf0 -set y_sshr 8'hf0 -set sh 4'd3 example003
sat_solve -set y 1'b1 example004
sat_solve -show rst,counter -set-at 3 y 1'b1 -seq 4 example004
sat -set y 1'b1 example001
sat -set y 1'b1 example002
sat -set y_sshl 8'hf0 -set y_sshr 8'hf0 -set sh 4'd3 example003
sat -set y 1'b1 example004
sat -show rst,counter -set-at 3 y 1'b1 -seq 4 example004
sat_solve -prove y 1'b0 -show rst,counter,y example004
sat_solve -prove y 1'b0 -show rst,counter,y -set-at 1 rst 1'b1 -seq 1 example004
sat -prove y 1'b0 -show rst,counter,y example004
sat -prove y 1'b0 -show rst,counter,y -set-at 1 rst 1'b1 -seq 1 example004