mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-07 09:55:20 +00:00
Code Activity

Some ASCII encoding fixes (comments and docs) by Larry Doolittle

Browse source
This commit is contained in:
Clifford Wolf 2015-08-13 09:30:20 +02:00
parent 667b015018
commit 08ad5409a2
4 changed files with 6 additions and 6 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
manual/APPNOTE_010_Verilog_to_BLIF.tex
View file

@ -100,7 +100,7 @@ regression testing Yosys.
\section{Getting Started} \section{Getting Started}
We start our tour with the Navré processor from yosys-bigsim. The Navré We start our tour with the Navr\'e processor from yosys-bigsim. The Navr\'e
processor \cite{navre} is an Open Source AVR clone. It is a single module ({\tt processor \cite{navre} is an Open Source AVR clone. It is a single module ({\tt
softusb\_navre}) in a single design file ({\tt softusb\_navre.v}). It also is softusb\_navre}) in a single design file ({\tt softusb\_navre.v}). It also is
using only features that map nicely to the BLIF format, for example it only using only features that map nicely to the BLIF format, for example it only
@ -226,7 +226,7 @@ further processed using custom commands. But in this case we don't want that.
\medskip \medskip
So now we have the final synthesis script for generating a BLIF file So now we have the final synthesis script for generating a BLIF file
for the Navré CPU: for the Navr\'e CPU:
\begin{figure}[H] \begin{figure}[H]
\begin{lstlisting}[language=sh] \begin{lstlisting}[language=sh]
@ -445,7 +445,7 @@ yosys-bigsim, a collection of real-world Verilog designs for regression testing
\url{https://github.com/cliffordwolf/yosys-bigsim} \url{https://github.com/cliffordwolf/yosys-bigsim}
\bibitem{navre} \bibitem{navre}
Sebastien Bourdeauducq. Navré AVR clone (8-bit RISC). \\ Sebastien Bourdeauducq. Navr\'e AVR clone (8-bit RISC). \\
\url{http://opencores.org/project,navre} \url{http://opencores.org/project,navre}
\bibitem{amber} \bibitem{amber}

2
passes/cmds/scc.cc
View file

@ -18,7 +18,7 @@
*/ */
// [[CITE]] Tarjan's strongly connected components algorithm // [[CITE]] Tarjan's strongly connected components algorithm
// Tarjan, R. E. (1972), "Depth-first search and linear graph algorithms", SIAM Journal on Computing 1 (2): 146–160, doi:10.1137/0201010 // Tarjan, R. E. (1972), "Depth-first search and linear graph algorithms", SIAM Journal on Computing 1 (2): 146-160, doi:10.1137/0201010
// http://en.wikipedia.org/wiki/Tarjan's_strongly_connected_components_algorithm // http://en.wikipedia.org/wiki/Tarjan's_strongly_connected_components_algorithm
#include "kernel/register.h" #include "kernel/register.h"

2
passes/techmap/abc.cc
View file

@ -26,7 +26,7 @@
// http://www.ece.cmu.edu/~ee760/760docs/blif.pdf // http://www.ece.cmu.edu/~ee760/760docs/blif.pdf
// [[CITE]] Kahn's Topological sorting algorithm // [[CITE]] Kahn's Topological sorting algorithm
// Kahn, Arthur B. (1962), "Topological sorting of large networks", Communications of the ACM 5 (11): 558–562, doi:10.1145/368996.369025 // Kahn, Arthur B. (1962), "Topological sorting of large networks", Communications of the ACM 5 (11): 558-562, doi:10.1145/368996.369025
// http://en.wikipedia.org/wiki/Topological_sorting // http://en.wikipedia.org/wiki/Topological_sorting
#define ABC_COMMAND_LIB "strash; scorr; ifraig; retime {D}; strash; dch -f; map {D}" #define ABC_COMMAND_LIB "strash; scorr; ifraig; retime {D}; strash; dch -f; map {D}"

2
tests/asicworld/code_hdl_models_up_counter.v
View file

@ -2,7 +2,7 @@
// Design Name : up_counter // Design Name : up_counter
// File Name : up_counter.v // File Name : up_counter.v
// Function : Up counter // Function : Up counter
// Coder  : Deepak // Coder : Deepak
//----------------------------------------------------- //-----------------------------------------------------
module up_counter ( module up_counter (
out , // Output of the counter out , // Output of the counter