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Some ASCII encoding fixes (comments and docs) by Larry Doolittle

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Clifford Wolf 2015-08-13 09:30:20 +02:00
parent 667b015018
commit 08ad5409a2
4 changed files with 6 additions and 6 deletions
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6
manual/APPNOTE_010_Verilog_to_BLIF.tex
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@ -100,7 +100,7 @@ regression testing Yosys.
\section{Getting Started}
We start our tour with the Navré processor from yosys-bigsim. The Navré
We start our tour with the Navr\'e processor from yosys-bigsim. The Navr\'e
processor \cite{navre} is an Open Source AVR clone. It is a single module ({\tt
softusb\_navre}) in a single design file ({\tt softusb\_navre.v}). It also is
using only features that map nicely to the BLIF format, for example it only
@ -226,7 +226,7 @@ further processed using custom commands. But in this case we don't want that.
\medskip
So now we have the final synthesis script for generating a BLIF file
for the Navré CPU:
for the Navr\'e CPU:
\begin{figure}[H]
\begin{lstlisting}[language=sh]
@ -445,7 +445,7 @@ yosys-bigsim, a collection of real-world Verilog designs for regression testing
\url{https://github.com/cliffordwolf/yosys-bigsim}
\bibitem{navre}
Sebastien Bourdeauducq. Navré AVR clone (8-bit RISC). \\
Sebastien Bourdeauducq. Navr\'e AVR clone (8-bit RISC). \\
\url{http://opencores.org/project,navre}
\bibitem{amber}