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Merge pull request #202 from Silimate/akashlevy/qor-pattern-passes
opt: recognize three QoR logic-depth patterns
This commit is contained in:
Akash Levy
GitHub
commit
087f5bd254
7 changed files with 1384 additions and 14 deletions
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@ -590,3 +590,170 @@ design -load postopt
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select -assert-min 1 w:*ffa_*
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design -reset
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log -pop
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# ============================================================================
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# Group G: coalesce-matrix variant (precomputed same_cat[i][k], raw-input en)
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# ============================================================================
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#
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# Some RTL precomputes a per-leader "same_cat[i][k]" mask (gated ONLY on the
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# leader's enable) and forward-coalesces the leader's slot into lane k without
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# re-checking en[k]. Disabled lanes after a same-category leader therefore
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# inherit that leader's slot (rather than 0). The pass detects this as the
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# enable-independent forward-coalescing variant. These modules also drive the
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# scan straight from a top-level request port (lane_en), exercising the
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# primary-input enable/broadcast candidate path.
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# G1: coalesce-matrix dsel-only, raw-input enable, N=8 (equiv).
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log -header "G1: coalesce-matrix allocator, raw-input enable, N=8 (equiv)"
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log -push
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design -reset
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read_verilog -sv <<EOF
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module top #(parameter N=8, NB=4, C=2, W=2) (
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input logic [N-1:0] lane_en,
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input logic [N*C-1:0] cat_flat,
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output logic [N*W-1:0] dsel_flat
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);
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logic [N-1:0] same_cat [0:N-1];
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always_comb begin
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for (int a=0;a<N;a++) begin
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same_cat[a] = '0;
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if (lane_en[a])
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for (int b=a;b<N;b++)
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if (cat_flat[a*C +: C]==cat_flat[b*C +: C]) same_cat[a][b] = 1'b1;
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end
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end
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logic [W-1:0] dsel [0:N-1];
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logic [NB-1:0] taken;
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logic [N-1:0] done;
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always_comb begin
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for (int i=0;i<N;i++) dsel[i] = '0;
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taken = '0; done = '0;
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for (int i=0;i<N;i++)
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if (lane_en[i])
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for (int j=0;j<NB;j++)
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if (!taken[j] && !done[i]) begin
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dsel[i] = W'(j); done[i] = 1'b1; taken[j] = 1'b1;
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for (int k=0;k<N;k++)
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if (same_cat[i][k]) begin dsel[k] = W'(j); done[k] = 1'b1; end
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end
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end
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for (genvar g=0;g<N;g++) assign dsel_flat[g*W +: W] = dsel[g];
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endmodule
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EOF
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hierarchy -top top
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proc
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opt
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check -assert
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equiv_opt -assert opt_first_fit_alloc
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design -load postopt
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# The coalesce variant fired (log shows "coalesce").
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select -assert-min 1 w:*ffa_*
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design -reset
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log -pop
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# G2: coalesce-matrix dsel + xbar, N=16 -- structural. Both deep cones must
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# collapse from the shared scan (dsel via the coalesce gather, xbar via the
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# per-slot field gather); full equiv at N=16 is SAT-hard (see group C).
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log -header "G2: coalesce-matrix dsel + xbar, N=16 structural"
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log -push
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design -reset
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read_verilog -sv <<EOF
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module top #(parameter N=16, NB=8, C=3, W=3, A=5) (
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input logic [N-1:0] lane_en,
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input logic [N*C-1:0] cat_flat,
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input logic [N-1:0] swap_bit,
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output logic [N*W-1:0] dsel_flat,
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output logic [32*A-1:0] xbar_flat
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);
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logic [N-1:0] same_cat [0:N-1];
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always_comb begin
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for (int a=0;a<N;a++) begin
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same_cat[a] = '0;
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if (lane_en[a])
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for (int b=a;b<N;b++)
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if (cat_flat[a*C +: C]==cat_flat[b*C +: C]) same_cat[a][b] = 1'b1;
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end
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end
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logic [NB-1:0] taken;
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logic [N-1:0] done;
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logic [W-1:0] dsel [0:N-1];
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logic [A-1:0] xbar [0:31];
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always_comb begin
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for (int i=0;i<N;i++) dsel[i] = '0;
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for (int i=0;i<32;i++) xbar[i] = '0;
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taken = '0; done = '0;
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for (int i=0;i<N;i++)
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if (lane_en[i])
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for (int j=0;j<NB;j++)
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if (!taken[j] && !done[i]) begin
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dsel[i] = W'(j); done[i] = 1'b1; taken[j] = 1'b1;
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for (int l=0;l<4;l++)
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xbar[(j*4)+l] = (A'(({2'b0,cat_flat[i*C +: C]}*4)+l)) ^ {3'b0, swap_bit[i], 1'b0};
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for (int k=0;k<N;k++)
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if (same_cat[i][k]) begin dsel[k] = W'(j); done[k] = 1'b1; end
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end
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end
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for (genvar g=0;g<N;g++) assign dsel_flat[g*W +: W] = dsel[g];
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for (genvar g=0;g<32;g++) assign xbar_flat[g*A +: A] = xbar[g];
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endmodule
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EOF
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hierarchy -top top
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proc
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memory -nomap -norom -nordff
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opt
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select -assert-min 1000 t:$mux
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opt_first_fit_alloc
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opt_clean
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select -assert-min 1 w:*ffa_*
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# The deep mux chains collapse and the xbar emits $bmux table-lookups.
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select -assert-max 200 t:$mux
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select -assert-min 1 t:$bmux
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design -reset
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log -pop
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# G3: coalesce-matrix but LAST-fit slot choice (scans free slots NB-1..0). The
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# same_cat coalescing is present but the slot assignment is not first-fit, so
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# neither the standard nor the coalesce fingerprint may match.
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log -header "G3: coalesce-matrix last-fit near-miss -> no rewrite"
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log -push
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design -reset
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read_verilog -sv <<EOF
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module top #(parameter N=8, NB=4, C=2, W=2) (
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input logic [N-1:0] lane_en,
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input logic [N*C-1:0] cat_flat,
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output logic [N*W-1:0] dsel_flat
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);
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logic [N-1:0] same_cat [0:N-1];
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always_comb begin
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for (int a=0;a<N;a++) begin
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same_cat[a] = '0;
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if (lane_en[a])
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for (int b=a;b<N;b++)
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if (cat_flat[a*C +: C]==cat_flat[b*C +: C]) same_cat[a][b] = 1'b1;
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end
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end
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logic [W-1:0] dsel [0:N-1];
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logic [NB-1:0] taken;
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logic [N-1:0] done;
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always_comb begin
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for (int i=0;i<N;i++) dsel[i] = '0;
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taken = '0; done = '0;
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for (int i=0;i<N;i++)
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if (lane_en[i])
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for (int j=NB-1;j>=0;j--)
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if (!taken[j] && !done[i]) begin
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dsel[i] = W'(j); done[i] = 1'b1; taken[j] = 1'b1;
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for (int k=0;k<N;k++)
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if (same_cat[i][k]) begin dsel[k] = W'(j); done[k] = 1'b1; end
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end
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end
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for (genvar g=0;g<N;g++) assign dsel_flat[g*W +: W] = dsel[g];
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endmodule
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EOF
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hierarchy -top top
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proc
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opt
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opt_first_fit_alloc
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select -assert-count 0 w:*ffa_*
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design -reset
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log -pop
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@ -672,3 +672,129 @@ equiv_opt -assert opt_prienc
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design -load postopt
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design -reset
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log -pop
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# ============================================================================
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# Group RR: round-robin (rotated priority) arbiters
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# ============================================================================
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#
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# grant / idx_next = first set request bit scanning upward (wrapping) from
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# just after a stored pointer idx_last. RTL spells this as a DEPTH-iteration
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# idx-- loop over req[idx] that elaborates into a serial mux/shift chain; the
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# pass replaces it with a log-depth threshold-mask + CTZ network.
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# RR1: power-of-2 DEPTH -- full sequential equivalence. Both grant and
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# idx_next collapse and every serial req[idx] $shiftx is removed.
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log -header "RR1: round-robin arbiter, DEPTH=16 (sequential equiv)"
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log -push
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design -reset
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read_verilog -sv <<EOF
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module test #(parameter int DEPTH = 16) (
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input logic clk,
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input logic rst_n,
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input logic [DEPTH-1:0] req,
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output logic [$clog2(DEPTH)-1:0] grant
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);
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typedef logic [$clog2(DEPTH)-1:0] idx_t;
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idx_t idx, idx_next, idx_last;
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always_comb begin
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idx = idx_last; idx_next = idx_last; grant = '0;
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for (int i = 0; i < DEPTH; i++) begin
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if (req[idx]) begin grant = idx; idx_next = idx; end
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if (idx == 0) idx = idx_t'(DEPTH-1); else idx--;
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end
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end
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always_ff @(posedge clk) begin
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if (!rst_n) idx_last <= '0;
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else if (idx_last != idx_next) idx_last <= idx_next;
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end
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endmodule
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EOF
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hierarchy -top test
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proc
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opt
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equiv_opt -assert -multiclock opt_prienc
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design -load postopt
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select -assert-min 1 w:*rr*
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select -assert-count 0 t:$shiftx
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design -reset
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log -pop
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# RR2: non-power-of-2 DEPTH -- combinational equivalence over the reachable
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# pointer range (idx_last in [0,DEPTH)). We rewrite one copy of the arbiter,
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# leave a reference copy untouched, and SAT-prove they agree once the pointer
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# input is mapped into [0,DEPTH).
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log -header "RR2: round-robin arbiter, DEPTH=13 (reachable-range equiv)"
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log -push
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design -reset
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read_verilog -sv <<EOF
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module rr_dut #(parameter int N=13, parameter int W=4) (
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input logic [N-1:0] req, input logic [W-1:0] s,
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output logic [W-1:0] grant, output logic [W-1:0] idx_next
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);
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always_comb begin
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logic [W-1:0] idx; idx=s; idx_next=s; grant='0;
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for (int i=0;i<N;i++) begin
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if (req[idx]) begin grant=idx; idx_next=idx; end
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if (idx==0) idx=W'(N-1); else idx--;
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end
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end
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endmodule
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EOF
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hierarchy -top rr_dut
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proc
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opt
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design -save rr_gold
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opt_prienc
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# The serial chain collapsed into the log-depth network.
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select -assert-min 1 w:*rr*
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select -assert-count 0 t:$shiftx
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design -save rr_gate
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design -reset
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design -copy-from rr_gold -as rr_ref rr_dut
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design -copy-from rr_gate -as rr_dut rr_dut
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read_verilog -sv <<EOF
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module tb #(parameter int N=13, parameter int W=4)(input logic [N-1:0] req, input logic [W-1:0] si);
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logic [W-1:0] s, g1,n1,g2,n2;
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assign s = (si >= N) ? (si - N) : si;
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rr_dut #(N,W) u1(.req(req),.s(s),.grant(g1),.idx_next(n1));
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rr_ref #(N,W) u2(.req(req),.s(s),.grant(g2),.idx_next(n2));
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always_comb begin
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assert (g1 == g2);
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assert (n1 == n2);
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end
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endmodule
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EOF
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hierarchy -top tb
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flatten
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chformal -lower
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opt -full
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sat -verify -prove-asserts -show-ports tb
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design -reset
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log -pop
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# RR3: negative -- a downward-scanning arbiter (opposite rotation) is a
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# different function and must not be rewritten as round-robin.
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log -header "RR3: downward-scan arbiter -> no round-robin rewrite"
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log -push
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design -reset
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read_verilog -sv <<EOF
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module test #(parameter int N=13, parameter int W=4) (
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input logic [N-1:0] req, input logic [W-1:0] s,
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output logic [W-1:0] grant
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);
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always_comb begin
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logic [W-1:0] idx; idx=s; grant='0;
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for (int i=0;i<N;i++) begin
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if (req[idx]) grant=idx;
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if (idx==W'(N-1)) idx='0; else idx++; // scans the other way
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end
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end
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endmodule
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EOF
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hierarchy -top test
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proc
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opt
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opt_prienc
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select -assert-count 0 w:*rr*
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design -reset
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log -pop
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240
tests/opt/opt_priokey.ys
Normal file
240
tests/opt/opt_priokey.ys
Normal file
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@ -0,0 +1,240 @@
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# Tests for opt_priokey
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#
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# The pass detects a serial "priority-by-key" set accumulator: several sources
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# each carry a small key and claim it if no earlier source already did. This
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# elaborates into a chain of dynamic-index reads/writes ($shiftx / $shift) into
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# a wide one-hot "taken" vector, whose depth grows with both the number of
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# sources P and the accumulator width S. Every dynamic read taken[key[j]] is
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# provably equal to the pairwise reduction
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#
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# OR over i<j of ( set_guard[i] & key[i] == key[j] )
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#
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# so the pass replaces each read with that compare reduction and drops the wide
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# dynamic indexing. Correctness of every rewrite is validated by an in-pass
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# ConstEval fingerprint over the reachable key range [0,S).
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#
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# Each group exercises a specific facet:
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# A: formal equivalence across (P,S) shapes (power-of-two S -> full equiv).
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# B: structural win -- the $shiftx chain is gone after the rewrite.
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# C: negative / no-op cases (no false rewrites).
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#
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# Convention: every object the pass emits is named with a `priokey_` suffix, so
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# `select w:*priokey*` is a reliable "did the rewrite fire" probe.
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# ============================================================================
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# Group A: formal equivalence (equiv_opt -assert)
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# ============================================================================
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# A1: P=3 sources into a 64-slot accumulator (SW=6, all keys reachable).
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log -header "A1: priority-by-key dedup P=3 S=64 (equiv)"
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log -push
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design -reset
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read_verilog -sv <<EOF
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module t #(parameter int P=3, parameter int S=64, parameter int SW=6)(
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input logic [P-1:0] act,
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input logic [P-1:0][SW-1:0] sel,
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input logic [P-1:0] src,
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output logic [P-1:0] win
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);
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logic [S-1:0] taken;
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always_comb begin
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taken = '0; win = '0;
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for (int i=0;i<P;i++)
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if (act[i] && !taken[sel[i]]) begin
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taken[sel[i]] = 1'b1;
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win[i] = src[i];
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end
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end
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endmodule
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EOF
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hierarchy -top t
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proc
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opt
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check -assert
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equiv_opt -assert opt_priokey
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design -load postopt
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select -assert-min 1 w:*priokey*
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select -assert-count 0 t:$shiftx
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design -reset
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log -pop
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# A2: P=4 sources into a 16-slot accumulator (SW=4).
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log -header "A2: priority-by-key dedup P=4 S=16 (equiv)"
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log -push
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design -reset
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read_verilog -sv <<EOF
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module t #(parameter int P=4, parameter int S=16, parameter int SW=4)(
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input logic [P-1:0] act,
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input logic [P-1:0][SW-1:0] sel,
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input logic [P-1:0] src,
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output logic [P-1:0] win
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);
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logic [S-1:0] taken;
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always_comb begin
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taken = '0; win = '0;
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for (int i=0;i<P;i++)
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if (act[i] && !taken[sel[i]]) begin
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taken[sel[i]] = 1'b1;
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win[i] = src[i];
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end
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end
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endmodule
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EOF
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hierarchy -top t
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proc
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opt
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check -assert
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equiv_opt -assert opt_priokey
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design -load postopt
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select -assert-min 1 w:*priokey*
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select -assert-count 0 t:$shiftx
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design -reset
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log -pop
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# A3: P=5 sources into an 8-slot accumulator (SW=3) -- deeper source chain.
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log -header "A3: priority-by-key dedup P=5 S=8 (equiv)"
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log -push
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design -reset
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read_verilog -sv <<EOF
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module t #(parameter int P=5, parameter int S=8, parameter int SW=3)(
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input logic [P-1:0] act,
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input logic [P-1:0][SW-1:0] sel,
|
||||
input logic [P-1:0] src,
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output logic [P-1:0] win
|
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);
|
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logic [S-1:0] taken;
|
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always_comb begin
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taken = '0; win = '0;
|
||||
for (int i=0;i<P;i++)
|
||||
if (act[i] && !taken[sel[i]]) begin
|
||||
taken[sel[i]] = 1'b1;
|
||||
win[i] = src[i];
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
EOF
|
||||
hierarchy -top t
|
||||
proc
|
||||
opt
|
||||
check -assert
|
||||
equiv_opt -assert opt_priokey
|
||||
design -load postopt
|
||||
select -assert-min 1 w:*priokey*
|
||||
select -assert-count 0 t:$shiftx
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
# ============================================================================
|
||||
# Group B: structural win (the dynamic-index chain disappears)
|
||||
# ============================================================================
|
||||
|
||||
# B1: P=6 sources, 64-slot accumulator. Before the rewrite the serial scan uses
|
||||
# per-source dynamic reads ($shiftx). After the rewrite those reads are gone,
|
||||
# replaced by pairwise $eq comparisons -- the QoR (depth) win.
|
||||
log -header "B1: priority-by-key structural, P=6 S=64"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog -sv <<EOF
|
||||
module t #(parameter int P=6, parameter int S=64, parameter int SW=6)(
|
||||
input logic [P-1:0] act,
|
||||
input logic [P-1:0][SW-1:0] sel,
|
||||
input logic [P-1:0] src,
|
||||
output logic [P-1:0] win
|
||||
);
|
||||
logic [S-1:0] taken;
|
||||
always_comb begin
|
||||
taken = '0; win = '0;
|
||||
for (int i=0;i<P;i++)
|
||||
if (act[i] && !taken[sel[i]]) begin
|
||||
taken[sel[i]] = 1'b1;
|
||||
win[i] = src[i];
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
EOF
|
||||
hierarchy -top t
|
||||
proc
|
||||
opt
|
||||
# Serial baseline: the dynamic-index reads are present.
|
||||
select -assert-min 1 t:$shiftx
|
||||
opt_priokey
|
||||
opt_clean
|
||||
# The wide dynamic indexing is gone, replaced by pairwise key comparisons.
|
||||
select -assert-count 0 t:$shiftx
|
||||
select -assert-min 1 t:$eq
|
||||
select -assert-min 1 w:*priokey*
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
# ============================================================================
|
||||
# Group C: negative / no-op cases (no false rewrites)
|
||||
# ============================================================================
|
||||
|
||||
# C1: the "taken" vector is a primary input, not a set accumulator rooted at 0.
|
||||
# The dynamic read has no traceable set history, so the pass must not fire.
|
||||
log -header "C1: non-accumulator dynamic read -> no rewrite"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog -sv <<EOF
|
||||
module t #(parameter int S=64, parameter int SW=6)(
|
||||
input logic [S-1:0] taken,
|
||||
input logic [SW-1:0] sel,
|
||||
output logic hit
|
||||
);
|
||||
assign hit = taken[sel];
|
||||
endmodule
|
||||
EOF
|
||||
hierarchy -top t
|
||||
proc
|
||||
opt
|
||||
opt_priokey
|
||||
select -assert-count 0 w:*priokey*
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
# C2: a plain per-lane passthrough -- no dynamic indexing at all.
|
||||
log -header "C2: per-lane passthrough -> no rewrite"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog -sv <<EOF
|
||||
module t #(parameter int P=4)(
|
||||
input logic [P-1:0] a,
|
||||
input logic [P-1:0] b,
|
||||
output logic [P-1:0] y
|
||||
);
|
||||
assign y = a & b;
|
||||
endmodule
|
||||
EOF
|
||||
hierarchy -top t
|
||||
proc
|
||||
opt
|
||||
opt_priokey
|
||||
select -assert-count 0 w:*priokey*
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
# C3: a dynamic write accumulator with NO conflict check -- every source
|
||||
# unconditionally sets its key and reads are absent (win is a direct index).
|
||||
# There is no taken[]-guarded read chain to rewrite.
|
||||
log -header "C3: unconditional writes, no guarded read -> no rewrite"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog -sv <<EOF
|
||||
module t #(parameter int P=3, parameter int S=16, parameter int SW=4)(
|
||||
input logic [P-1:0][SW-1:0] sel,
|
||||
output logic [S-1:0] taken
|
||||
);
|
||||
always_comb begin
|
||||
taken = '0;
|
||||
for (int i=0;i<P;i++)
|
||||
taken[sel[i]] = 1'b1;
|
||||
end
|
||||
endmodule
|
||||
EOF
|
||||
hierarchy -top t
|
||||
proc
|
||||
opt
|
||||
opt_priokey
|
||||
select -assert-count 0 w:*priokey*
|
||||
design -reset
|
||||
log -pop
|
||||
Loading…
Add table
Add a link
Reference in a new issue