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https://github.com/YosysHQ/yosys
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Implemented "rename -enumerate -pattern"
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parent
e70480655e
commit
084685f480
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@ -58,10 +58,12 @@ struct RenamePass : public Pass {
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log("by this command.\n");
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log("by this command.\n");
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log("\n");
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log("\n");
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log("\n");
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log("\n");
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log(" rename -enumerate [selection]\n");
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log(" rename -enumerate [-pattern <pattern>] [selection]\n");
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log("\n");
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log("\n");
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log("Assign short auto-generated names to all selected wires and cells with private\n");
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log("Assign short auto-generated names to all selected wires and cells with private\n");
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log("names.\n");
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log("names. The -pattern option can be used to set the pattern for the new names.\n");
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log("The character %% in the pattern is replaced with a integer number. The default\n");
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log("pattern is '_%%_'.\n");
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log("\n");
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log("\n");
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log(" rename -hide [selection]\n");
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log(" rename -hide [selection]\n");
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log("\n");
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log("\n");
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@ -71,6 +73,7 @@ struct RenamePass : public Pass {
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}
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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{
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std::string pattern_prefix = "_", pattern_suffix = "_";
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bool flag_enumerate = false;
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bool flag_enumerate = false;
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bool flag_hide = false;
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bool flag_hide = false;
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bool got_mode = false;
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bool got_mode = false;
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@ -89,6 +92,12 @@ struct RenamePass : public Pass {
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got_mode = true;
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got_mode = true;
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continue;
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continue;
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}
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}
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if (arg == "-pattern" && argidx+1 < args.size() && args[argidx+1].find('%') != std::string::npos) {
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int pos = args[++argidx].find('%');
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pattern_prefix = args[argidx].substr(0, pos);
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pattern_suffix = args[argidx].substr(pos+1);
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continue;
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}
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break;
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break;
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}
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}
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@ -107,7 +116,7 @@ struct RenamePass : public Pass {
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std::map<RTLIL::IdString, RTLIL::Wire*> new_wires;
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std::map<RTLIL::IdString, RTLIL::Wire*> new_wires;
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for (auto &it : module->wires_) {
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for (auto &it : module->wires_) {
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if (it.first[0] == '$' && design->selected(module, it.second))
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if (it.first[0] == '$' && design->selected(module, it.second))
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do it.second->name = stringf("\\_%d_", counter++);
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do it.second->name = stringf("\\%s%d%s", pattern_prefix.c_str(), counter++, pattern_suffix.c_str());
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while (module->count_id(it.second->name) > 0);
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while (module->count_id(it.second->name) > 0);
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new_wires[it.second->name] = it.second;
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new_wires[it.second->name] = it.second;
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}
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}
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@ -116,7 +125,7 @@ struct RenamePass : public Pass {
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std::map<RTLIL::IdString, RTLIL::Cell*> new_cells;
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std::map<RTLIL::IdString, RTLIL::Cell*> new_cells;
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for (auto &it : module->cells_) {
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for (auto &it : module->cells_) {
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if (it.first[0] == '$' && design->selected(module, it.second))
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if (it.first[0] == '$' && design->selected(module, it.second))
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do it.second->name = stringf("\\_%d_", counter++);
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do it.second->name = stringf("\\%s%d%s", pattern_prefix.c_str(), counter++, pattern_suffix.c_str());
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while (module->count_id(it.second->name) > 0);
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while (module->count_id(it.second->name) > 0);
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new_cells[it.second->name] = it.second;
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new_cells[it.second->name] = it.second;
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}
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}
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