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Merge branch 'YosysHQ:main' into main

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This commit is contained in:
Akash Levy 2025-07-15 00:04:28 -04:00 • committed by GitHub
commit 082adf8684
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28 changed files with 1574 additions and 143 deletions
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12
kernel/log.cc
View file

@ -664,15 +664,9 @@ const char *log_const(const RTLIL::Const &value, bool autoint)
const char *log_id(const RTLIL::IdString &str)
{
log_id_cache.push_back(strdup(str.c_str()));
const char *p = log_id_cache.back();
if (p[0] != '\\')
return p;
if (p[1] == '$' || p[1] == '\\' || p[1] == 0)
return p;
if (p[1] >= '0' && p[1] <= '9')
return p;
return p+1;
std::string unescaped = RTLIL::unescape_id(str);
log_id_cache.push_back(strdup(unescaped.c_str()));
return log_id_cache.back();
}
const char *log_str(const char *str)

13
kernel/rtlil.cc
View file

@ -386,7 +386,7 @@ bool RTLIL::Const::convertible_to_int(bool is_signed) const
{
auto size = get_min_size(is_signed);
if (size <= 0)
if (size < 0)
return false;
// If it fits in 31 bits it is definitely convertible
@ -5580,6 +5580,9 @@ bool RTLIL::SigSpec::convertible_to_int(bool is_signed) const
if (!is_fully_const())
return false;
if (empty())
return true;
return RTLIL::Const(chunks_[0].data).convertible_to_int(is_signed);
}
@ -5591,6 +5594,9 @@ std::optional<int> RTLIL::SigSpec::try_as_int(bool is_signed) const
if (!is_fully_const())
return std::nullopt;
if (empty())
return 0;
return RTLIL::Const(chunks_[0].data).try_as_int(is_signed);
}
@ -5600,7 +5606,10 @@ int RTLIL::SigSpec::as_int_saturating(bool is_signed) const
pack();
log_assert(is_fully_const() && GetSize(chunks_) <= 1);
log_assert(!empty());
if (empty())
return 0;
return RTLIL::Const(chunks_[0].data).as_int_saturating(is_signed);
}

4
kernel/satgen.h
View file

@ -101,7 +101,9 @@ struct SatGen
else
vec.push_back(bit == (undef_mode ? RTLIL::State::Sx : RTLIL::State::S1) ? ez->CONST_TRUE : ez->CONST_FALSE);
} else {
std::string name = pf + (bit.wire->width == 1 ? stringf("%s", log_id(bit.wire)) : stringf("%s [%d]", log_id(bit.wire->name), bit.offset));
std::string wire_name = RTLIL::unescape_id(bit.wire->name);
std::string name = pf +
(bit.wire->width == 1 ? wire_name : stringf("%s [%d]", wire_name.c_str(), bit.offset));
vec.push_back(ez->frozen_literal(name));
imported_signals[pf][bit] = vec.back();
}