mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-23 09:05:32 +00:00
Code Activity

Towards Xilinx bram support

Browse source
This commit is contained in:
Clifford Wolf 2015-01-06 14:26:51 +01:00
parent 9c7f47bbd5
commit 081e1a49f8
3 changed files with 42 additions and 14 deletions
Download patch file Download diff file Expand all files Collapse all files

2
passes/memory/memory_bram.cc
View file

@ -356,7 +356,7 @@ bool replace_cell(Cell *cell, const rules_t::bram_t &bram, const rules_t::match_
for (int i = 0; i < fillbits; i++) {
for (int j = 0; j < wr_ports; j++) {
new_wr_en[j].append(fillbit);
new_wr_data[j].append(State::Sx);
new_wr_data[j].append(State::S0);
}
for (int j = 0; j < rd_ports; j++)
new_rd_data[j].append(State::Sx);