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ecp5: add support for both 1364.1 and LSE RAM/ROM attributes.

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This commit tries to carefully follow the documented behavior of LSE
and Synplify. It will use `syn_ramstyle` attribute if there are any
write ports, and `syn_romstyle` attribute otherwise.
  * LSE supports both `syn_ramstyle` and `syn_romstyle`.
  * Synplify only supports `syn_ramstyle`, with same values as LSE.
  * Synplify also supports `syn_rw_conflict_logic`, which is not
    documented as supported for LSE.

Limitations of the Yosys implementation:
  * LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"`
    syntax to turn off insertion of transparency logic. There is
    currently no way to support multiple valued attributes in
    memory_bram. It is also not clear if that is a good idea, since
    it can cause sim/synth mismatches.
  * LSE/Synplify/1364.1 support block ROM inference from full case
    statements. Yosys does not currently perform this transformation.
  * LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes
    from the module to the inner memories. There is currently no way
    to do this in Yosys (attrmvcp only works on cells and wires).
This commit is contained in:
whitequark 2020-01-01 08:27:47 +00:00
parent 3f4460a186
commit 081d9318bc
5 changed files with 376 additions and 5 deletions
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10
tests/arch/common/blockrom.v
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@ -10,16 +10,16 @@ module sync_rom #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
reg [WORD:0] data_out_r;
reg [WORD:0] memory [0:DEPTH];
integer i,j = 16'hACE1;
integer i,j = 64'hF4B1CA8127865242;
initial
for (i = 0; i <= DEPTH; i++) begin
// In case this ROM will be implemented in fabric: fill the memory with some data
// uncorrelated with the address, or Yosys might see through the ruse and e.g. not
// emit any LUTs at all for `memory[i] = i;`, just a latch.
memory[i] = j;
j = j ^ (j >> 7);
j = j ^ (j << 9);
j = j ^ (j >> 13);
memory[i] = j * 64'h2545F4914F6CDD1D;
j = j ^ (j >> 12);
j = j ^ (j << 25);
j = j ^ (j >> 27);
end
always @(posedge clk) begin