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Simplify some RTLIL destructors

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No change in behaviour, but use range-based for loops instead of
iterators.
This commit is contained in:
Rupert Swarbrick 2020-04-20 15:58:30 +01:00 • committed by Zachary Snow
parent 801ecc0e1d
commit 081111714e
1 changed files with 10 additions and 10 deletions
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20
kernel/rtlil.cc
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@ -571,8 +571,8 @@ RTLIL::Design::Design()
RTLIL::Design::~Design()
{
for (auto it = modules_.begin(); it != modules_.end(); ++it)
delete it->second;
for (auto &pr : modules_)
delete pr.second;
for (auto n : verilog_packages)
delete n;
for (auto n : verilog_globals)
@ -864,14 +864,14 @@ RTLIL::Module::Module()
RTLIL::Module::~Module()
{
for (auto it = wires_.begin(); it != wires_.end(); ++it)
delete it->second;
for (auto it = memories.begin(); it != memories.end(); ++it)
delete it->second;
for (auto it = cells_.begin(); it != cells_.end(); ++it)
delete it->second;
for (auto it = processes.begin(); it != processes.end(); ++it)
delete it->second;
for (auto &pr : wires_)
delete pr.second;
for (auto &pr : memories)
delete pr.second;
for (auto &pr : cells_)
delete pr.second;
for (auto &pr : processes)
delete pr.second;
#ifdef WITH_PYTHON
RTLIL::Module::get_all_modules()->erase(hashidx_);
#endif