From 2ef2e2c040d9ff299f1bc6daca891a1236ed877e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 22 Nov 2019 16:41:05 -0800
Subject: [PATCH 1/3] Add testcase
---
tests/various/submod.ys | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
create mode 100644 tests/various/submod.ys
diff --git a/tests/various/submod.ys b/tests/various/submod.ys
new file mode 100644
index 000000000..54455b580
--- /dev/null
+++ b/tests/various/submod.ys
@@ -0,0 +1,26 @@
+read_verilog <<EOT
+module top(input a, output [1:0] b);
+wire c;
+(* submod="bar" *) sub s1(a, c);
+assign b[0] = c;
+endmodule
+
+module sub(input a, output c);
+assign c = a;
+endmodule
+EOT
+
+hierarchy -top top
+proc
+design -save gold
+submod
+flatten
+
+design -stash gate
+
+design -import gold -as gold
+design -import gate -as gate
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
+
From 6a52897aeeff3e452884512470f21fa898b9e780 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 22 Nov 2019 16:46:26 -0800
Subject: [PATCH 2/3] sigmap(wire) should inherit port_output status of POs
---
passes/hierarchy/submod.cc | 20 +++++++++++++++++++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc
index ec242aa1f..982558fb2 100644
--- a/passes/hierarchy/submod.cc
+++ b/passes/hierarchy/submod.cc
@@ -20,6 +20,7 @@
#include "kernel/register.h"
#include "kernel/celltypes.h"
#include "kernel/log.h"
+#include "kernel/sigtools.h"
#include <stdlib.h>
#include <stdio.h>
#include <set>
@@ -32,6 +33,7 @@ struct SubmodWorker
CellTypes ct;
RTLIL::Design *design;
RTLIL::Module *module;
+ pool<Wire*> outputs;
bool copy_mode;
std::string opt_name;
@@ -125,7 +127,7 @@ struct SubmodWorker
if (wire->port_input)
flags.is_ext_driven = true;
- if (wire->port_output)
+ if (wire->port_output || outputs.count(wire))
flags.is_ext_used = true;
bool new_wire_port_input = false;
@@ -219,6 +221,22 @@ struct SubmodWorker
ct.setup_stdcells_mem();
ct.setup_design(design);
+ SigMap sigmap(module);
+ for (auto port : module->ports) {
+ auto wire = module->wire(port);
+ if (!wire->port_output)
+ continue;
+ auto sig = sigmap(wire);
+ for (auto c : sig.chunks()) {
+ if (!c.wire)
+ continue;
+ if (c.wire == wire)
+ continue;
+ outputs.insert(c.wire);
+ log_dump(c.wire->name);
+ }
+ }
+
if (opt_name.empty())
{
for (auto &it : module->wires_)
From 8779faf7891cf1fc394204b12ad1a0e403d22c6b Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 22 Nov 2019 16:50:09 -0800
Subject: [PATCH 3/3] Cleanup spacing
---
tests/various/submod.ys | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/tests/various/submod.ys b/tests/various/submod.ys
index 54455b580..271a8edef 100644
--- a/tests/various/submod.ys
+++ b/tests/various/submod.ys
@@ -13,9 +13,9 @@ EOT
hierarchy -top top
proc
design -save gold
+
submod
flatten
-
design -stash gate
design -import gold -as gold
@@ -23,4 +23,3 @@ design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter
-