mirror of
				https://github.com/YosysHQ/yosys
				synced 2025-10-30 19:22:31 +00:00 
			
		
		
		
	rtlil: handle all-zeros case in Const::compress
This commit is contained in:
		
							parent
							
								
									4cd2e04da4
								
							
						
					
					
						commit
						07fb8af05b
					
				
					 1 changed files with 9 additions and 7 deletions
				
			
		|  | @ -293,13 +293,15 @@ void RTLIL::Const::compress(bool is_signed) | |||
| 
 | ||||
| 	size_t idx = bits.size(); | ||||
| 	while (idx > 0 && bits[idx -1] == leading_bit) { | ||||
|         --idx; | ||||
| 		idx--; | ||||
| 	} | ||||
| 
 | ||||
| 	// signed needs one leading bit
 | ||||
| 	if (is_signed && idx < bits.size()) { | ||||
|         ++idx; | ||||
| 		idx++; | ||||
| 	} | ||||
| 	// must be at least one bit
 | ||||
| 	idx = (idx == 0) ? 1 : idx; | ||||
| 
 | ||||
| 	bits.erase(bits.begin() + idx, bits.end()); | ||||
| } | ||||
|  |  | |||
		Loading…
	
	Add table
		Add a link
		
	
		Reference in a new issue