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rtlil: handle all-zeros case in Const::compress

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Philippe Sauter 2024-09-20 13:56:14 +02:00 committed by Emil J. Tywoniak
parent 4cd2e04da4
commit 07fb8af05b
1 changed files with 9 additions and 7 deletions
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16
kernel/rtlil.cc
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@ -286,20 +286,22 @@ void RTLIL::Const::compress(bool is_signed)
// back to front (MSB to LSB) // back to front (MSB to LSB)
RTLIL::State leading_bit; RTLIL::State leading_bit;
if(is_signed) if (is_signed)
leading_bit = (bits.back() == RTLIL::State::Sx) ? RTLIL::State::S0 : bits.back(); leading_bit = (bits.back() == RTLIL::State::Sx) ? RTLIL::State::S0 : bits.back();
else else
leading_bit = RTLIL::State::S0; leading_bit = RTLIL::State::S0;
size_t idx = bits.size(); size_t idx = bits.size();
while (idx > 0 && bits[idx -1] == leading_bit) { while (idx > 0 && bits[idx -1] == leading_bit) {
--idx; idx--;
} }
// signed needs one leading bit // signed needs one leading bit
if (is_signed && idx < bits.size()) { if (is_signed && idx < bits.size()) {
++idx; idx++;
} }
// must be at least one bit
idx = (idx == 0) ? 1 : idx;
bits.erase(bits.begin() + idx, bits.end()); bits.erase(bits.begin() + idx, bits.end());
} }