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https://github.com/YosysHQ/yosys
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opt_reduce: Add $bmux and $demux optimization patterns.
This commit is contained in:
Marcelina Kościelnicka
parent
772d137bfa
commit
07a657fb0c
3 changed files with 548 additions and 63 deletions
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@ -100,7 +100,7 @@ struct OptReduceWorker
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return;
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}
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void opt_mux(RTLIL::Cell *cell)
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void opt_pmux(RTLIL::Cell *cell)
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{
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RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A));
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RTLIL::SigSpec sig_b = assign_map(cell->getPort(ID::B));
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@ -141,20 +141,20 @@ struct OptReduceWorker
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handled_sig.insert(this_b);
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}
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if (new_sig_s.size() != sig_s.size()) {
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if (new_sig_s.size() == 0)
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{
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module->connect(cell->getPort(ID::Y), cell->getPort(ID::A));
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assign_map.add(cell->getPort(ID::Y), cell->getPort(ID::A));
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module->remove(cell);
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did_something = true;
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total_count++;
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return;
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}
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if (new_sig_s.size() != sig_s.size() || (new_sig_s.size() == 1 && cell->type == ID($pmux))) {
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log(" New ctrl vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_s));
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did_something = true;
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total_count++;
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}
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if (new_sig_s.size() == 0)
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{
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module->connect(RTLIL::SigSig(cell->getPort(ID::Y), cell->getPort(ID::A)));
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assign_map.add(cell->getPort(ID::Y), cell->getPort(ID::A));
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module->remove(cell);
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}
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else
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{
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cell->setPort(ID::B, new_sig_b);
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cell->setPort(ID::S, new_sig_s);
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if (new_sig_s.size() > 1) {
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@ -166,81 +166,347 @@ struct OptReduceWorker
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}
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}
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void opt_mux_bits(RTLIL::Cell *cell)
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void opt_bmux(RTLIL::Cell *cell)
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{
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std::vector<RTLIL::SigBit> sig_a = assign_map(cell->getPort(ID::A)).to_sigbit_vector();
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std::vector<RTLIL::SigBit> sig_b = assign_map(cell->getPort(ID::B)).to_sigbit_vector();
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std::vector<RTLIL::SigBit> sig_y = assign_map(cell->getPort(ID::Y)).to_sigbit_vector();
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RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A));
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RTLIL::SigSpec sig_s = assign_map(cell->getPort(ID::S));
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int width = cell->getParam(ID::WIDTH).as_int();
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RTLIL::SigSpec new_sig_a, new_sig_s;
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dict<RTLIL::SigBit, int> handled_bits;
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// 0 and up: index of new_sig_s bit
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// -1: const 0
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// -2: const 1
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std::vector<int> swizzle;
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for (int i = 0; i < sig_s.size(); i++)
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{
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SigBit bit = sig_s[i];
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if (bit == State::S0) {
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swizzle.push_back(-1);
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} else if (bit == State::S1) {
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swizzle.push_back(-2);
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} else {
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auto it = handled_bits.find(bit);
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if (it == handled_bits.end()) {
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int new_idx = GetSize(new_sig_s);
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new_sig_s.append(bit);
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handled_bits[bit] = new_idx;
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swizzle.push_back(new_idx);
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} else {
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swizzle.push_back(it->second);
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}
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}
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}
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for (int i = 0; i < (1 << GetSize(new_sig_s)); i++) {
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int idx = 0;
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for (int j = 0; j < GetSize(sig_s); j++) {
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if (swizzle[j] == -1) {
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// const 0.
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} else if (swizzle[j] == -2) {
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// const 1.
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idx |= 1 << j;
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} else {
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if (i & 1 << swizzle[j])
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idx |= 1 << j;
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}
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}
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new_sig_a.append(sig_a.extract(idx * width, width));
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}
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if (new_sig_s.size() == 0)
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{
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module->connect(cell->getPort(ID::Y), new_sig_a);
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assign_map.add(cell->getPort(ID::Y), new_sig_a);
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module->remove(cell);
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did_something = true;
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total_count++;
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return;
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}
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if (new_sig_s.size() == 1)
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{
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cell->type = ID($mux);
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cell->setPort(ID::A, new_sig_a.extract(0, width));
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cell->setPort(ID::B, new_sig_a.extract(width, width));
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cell->setPort(ID::S, new_sig_s);
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cell->parameters.erase(ID::S_WIDTH);
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did_something = true;
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total_count++;
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return;
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}
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if (new_sig_s.size() != sig_s.size()) {
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log(" New ctrl vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_s));
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did_something = true;
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total_count++;
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cell->setPort(ID::A, new_sig_a);
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cell->setPort(ID::S, new_sig_s);
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cell->parameters[ID::S_WIDTH] = RTLIL::Const(new_sig_s.size());
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}
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}
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void opt_demux(RTLIL::Cell *cell)
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{
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RTLIL::SigSpec sig_y = assign_map(cell->getPort(ID::Y));
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RTLIL::SigSpec sig_s = assign_map(cell->getPort(ID::S));
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int width = cell->getParam(ID::WIDTH).as_int();
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RTLIL::SigSpec new_sig_y, new_sig_s;
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dict<RTLIL::SigBit, int> handled_bits;
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// 0 and up: index of new_sig_s bit
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// -1: const 0
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// -2: const 1
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std::vector<int> swizzle;
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for (int i = 0; i < sig_s.size(); i++)
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{
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SigBit bit = sig_s[i];
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if (bit == State::S0) {
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swizzle.push_back(-1);
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} else if (bit == State::S1) {
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swizzle.push_back(-2);
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} else {
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auto it = handled_bits.find(bit);
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if (it == handled_bits.end()) {
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int new_idx = GetSize(new_sig_s);
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new_sig_s.append(bit);
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handled_bits[bit] = new_idx;
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swizzle.push_back(new_idx);
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} else {
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swizzle.push_back(it->second);
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}
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}
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}
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pool<int> nonzero_idx;
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for (int i = 0; i < (1 << GetSize(new_sig_s)); i++) {
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int idx = 0;
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for (int j = 0; j < GetSize(sig_s); j++) {
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if (swizzle[j] == -1) {
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// const 0.
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} else if (swizzle[j] == -2) {
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// const 1.
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idx |= 1 << j;
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} else {
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if (i & 1 << swizzle[j])
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idx |= 1 << j;
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}
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}
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log_assert(!nonzero_idx.count(idx));
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nonzero_idx.insert(idx);
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new_sig_y.append(sig_y.extract(idx * width, width));
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}
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if (new_sig_s.size() == sig_s.size() && sig_s.size() > 0)
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return;
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log(" New ctrl vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_s));
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did_something = true;
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total_count++;
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for (int i = 0; i < (1 << GetSize(sig_s)); i++) {
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if (!nonzero_idx.count(i)) {
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SigSpec slice = sig_y.extract(i * width, width);
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module->connect(slice, Const(State::S0, width));
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assign_map.add(slice, Const(State::S0, width));
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}
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}
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if (new_sig_s.size() == 0)
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{
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module->connect(new_sig_y, cell->getPort(ID::A));
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assign_map.add(new_sig_y, cell->getPort(ID::A));
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module->remove(cell);
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}
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else
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{
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cell->setPort(ID::S, new_sig_s);
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cell->setPort(ID::Y, new_sig_y);
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cell->parameters[ID::S_WIDTH] = RTLIL::Const(new_sig_s.size());
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}
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}
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bool opt_mux_bits(RTLIL::Cell *cell)
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{
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SigSpec sig_a = assign_map(cell->getPort(ID::A));
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SigSpec sig_b;
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SigSpec sig_y = assign_map(cell->getPort(ID::Y));
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int width = GetSize(sig_y);
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if (cell->type != ID($bmux))
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sig_b = assign_map(cell->getPort(ID::B));
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std::vector<RTLIL::SigBit> new_sig_y;
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RTLIL::SigSig old_sig_conn;
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std::vector<std::vector<RTLIL::SigBit>> consolidated_in_tuples;
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std::map<std::vector<RTLIL::SigBit>, RTLIL::SigBit> consolidated_in_tuples_map;
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dict<SigSpec, SigBit> consolidated_in_tuples;
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std::vector<int> swizzle;
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for (int i = 0; i < int(sig_y.size()); i++)
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for (int i = 0; i < width; i++)
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{
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std::vector<RTLIL::SigBit> in_tuple;
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SigSpec in_tuple;
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bool all_tuple_bits_same = true;
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in_tuple.push_back(sig_a.at(i));
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for (int j = i; j < int(sig_b.size()); j += int(sig_a.size())) {
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if (sig_b.at(j) != sig_a.at(i))
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in_tuple.append(sig_a[i]);
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for (int j = i; j < GetSize(sig_a); j += width) {
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in_tuple.append(sig_a[j]);
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if (sig_a[j] != in_tuple[0])
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all_tuple_bits_same = false;
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}
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for (int j = i; j < GetSize(sig_b); j += width) {
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in_tuple.append(sig_b[j]);
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if (sig_b[j] != in_tuple[0])
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all_tuple_bits_same = false;
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in_tuple.push_back(sig_b.at(j));
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}
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if (all_tuple_bits_same)
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{
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old_sig_conn.first.append(sig_y.at(i));
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old_sig_conn.second.append(sig_a.at(i));
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old_sig_conn.first.append(sig_y[i]);
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old_sig_conn.second.append(sig_a[i]);
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continue;
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}
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else if (consolidated_in_tuples_map.count(in_tuple))
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auto it = consolidated_in_tuples.find(in_tuple);
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if (it == consolidated_in_tuples.end())
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{
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old_sig_conn.first.append(sig_y.at(i));
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old_sig_conn.second.append(consolidated_in_tuples_map.at(in_tuple));
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consolidated_in_tuples[in_tuple] = sig_y[i];
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swizzle.push_back(i);
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}
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else
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{
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consolidated_in_tuples_map[in_tuple] = sig_y.at(i);
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consolidated_in_tuples.push_back(in_tuple);
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new_sig_y.push_back(sig_y.at(i));
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old_sig_conn.first.append(sig_y[i]);
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old_sig_conn.second.append(it->second);
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}
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}
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if (new_sig_y.size() != sig_y.size())
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if (GetSize(swizzle) != width)
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{
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log(" Consolidated identical input bits for %s cell %s:\n", cell->type.c_str(), cell->name.c_str());
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log(" Old ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort(ID::A)),
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log_signal(cell->getPort(ID::B)), log_signal(cell->getPort(ID::Y)));
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cell->setPort(ID::A, RTLIL::SigSpec());
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for (auto &in_tuple : consolidated_in_tuples) {
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RTLIL::SigSpec new_a = cell->getPort(ID::A);
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new_a.append(in_tuple.at(0));
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cell->setPort(ID::A, new_a);
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if (cell->type != ID($bmux)) {
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log(" Old ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort(ID::A)),
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log_signal(cell->getPort(ID::B)), log_signal(cell->getPort(ID::Y)));
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} else {
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log(" Old ports: A=%s, Y=%s\n", log_signal(cell->getPort(ID::A)),
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log_signal(cell->getPort(ID::Y)));
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}
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cell->setPort(ID::B, RTLIL::SigSpec());
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for (int i = 1; i <= cell->getPort(ID::S).size(); i++)
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for (auto &in_tuple : consolidated_in_tuples) {
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RTLIL::SigSpec new_b = cell->getPort(ID::B);
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new_b.append(in_tuple.at(i));
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cell->setPort(ID::B, new_b);
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if (swizzle.empty()) {
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module->remove(cell);
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} else {
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SigSpec new_sig_a;
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for (int i = 0; i < GetSize(sig_a); i += width)
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for (int j: swizzle)
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new_sig_a.append(sig_a[i+j]);
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cell->setPort(ID::A, new_sig_a);
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if (cell->type != ID($bmux)) {
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SigSpec new_sig_b;
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for (int i = 0; i < GetSize(sig_b); i += width)
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for (int j: swizzle)
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new_sig_b.append(sig_b[i+j]);
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cell->setPort(ID::B, new_sig_b);
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}
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cell->parameters[ID::WIDTH] = RTLIL::Const(new_sig_y.size());
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cell->setPort(ID::Y, new_sig_y);
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SigSpec new_sig_y;
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for (int j: swizzle)
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new_sig_y.append(sig_y[j]);
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cell->setPort(ID::Y, new_sig_y);
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cell->parameters[ID::WIDTH] = RTLIL::Const(GetSize(swizzle));
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if (cell->type != ID($bmux)) {
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log(" New ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort(ID::A)),
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log_signal(cell->getPort(ID::B)), log_signal(cell->getPort(ID::Y)));
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} else {
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log(" New ports: A=%s, Y=%s\n", log_signal(cell->getPort(ID::A)),
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log_signal(cell->getPort(ID::Y)));
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}
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}
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log(" New ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort(ID::A)),
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log_signal(cell->getPort(ID::B)), log_signal(cell->getPort(ID::Y)));
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log(" New connections: %s = %s\n", log_signal(old_sig_conn.first), log_signal(old_sig_conn.second));
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module->connect(old_sig_conn);
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did_something = true;
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total_count++;
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}
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return swizzle.empty();
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}
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bool opt_demux_bits(RTLIL::Cell *cell) {
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SigSpec sig_a = assign_map(cell->getPort(ID::A));
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SigSpec sig_y = assign_map(cell->getPort(ID::Y));
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int width = GetSize(sig_a);
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RTLIL::SigSig old_sig_conn;
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dict<SigBit, int> handled_bits;
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std::vector<int> swizzle;
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for (int i = 0; i < width; i++)
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{
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if (sig_a[i] == State::S0)
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{
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for (int j = i; j < GetSize(sig_y); j += width)
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{
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old_sig_conn.first.append(sig_y[j]);
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old_sig_conn.second.append(State::S0);
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}
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continue;
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}
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auto it = handled_bits.find(sig_a[i]);
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if (it == handled_bits.end())
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{
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handled_bits[sig_a[i]] = i;
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swizzle.push_back(i);
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}
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else
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{
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for (int j = 0; j < GetSize(sig_y); j += width)
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{
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old_sig_conn.first.append(sig_y[i+j]);
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old_sig_conn.second.append(sig_y[it->second+j]);
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}
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}
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}
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if (GetSize(swizzle) != width)
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{
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log(" Consolidated identical input bits for %s cell %s:\n", cell->type.c_str(), cell->name.c_str());
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log(" Old ports: A=%s, Y=%s\n", log_signal(cell->getPort(ID::A)),
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log_signal(cell->getPort(ID::Y)));
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if (swizzle.empty()) {
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module->remove(cell);
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} else {
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SigSpec new_sig_a;
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for (int j: swizzle)
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new_sig_a.append(sig_a[j]);
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cell->setPort(ID::A, new_sig_a);
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SigSpec new_sig_y;
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for (int i = 0; i < GetSize(sig_y); i += width)
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for (int j: swizzle)
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new_sig_y.append(sig_y[i+j]);
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cell->setPort(ID::Y, new_sig_y);
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cell->parameters[ID::WIDTH] = RTLIL::Const(GetSize(swizzle));
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log(" New ports: A=%s, Y=%s\n", log_signal(cell->getPort(ID::A)),
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log_signal(cell->getPort(ID::Y)));
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}
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|
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log(" New connections: %s = %s\n", log_signal(old_sig_conn.first), log_signal(old_sig_conn.second));
|
||||
module->connect(old_sig_conn);
|
||||
|
||||
did_something = true;
|
||||
total_count++;
|
||||
}
|
||||
return swizzle.empty();
|
||||
}
|
||||
|
||||
OptReduceWorker(RTLIL::Design *design, RTLIL::Module *module, bool do_fine) :
|
||||
|
|
@ -309,20 +575,31 @@ struct OptReduceWorker
|
|||
|
||||
// merge identical inputs on $mux and $pmux cells
|
||||
|
||||
std::vector<RTLIL::Cell*> cells;
|
||||
|
||||
for (auto &it : module->cells_)
|
||||
if ((it.second->type == ID($mux) || it.second->type == ID($pmux)) && design->selected(module, it.second))
|
||||
cells.push_back(it.second);
|
||||
|
||||
for (auto cell : cells)
|
||||
for (auto cell : module->selected_cells())
|
||||
{
|
||||
if (!cell->type.in(ID($mux), ID($pmux), ID($bmux), ID($demux)))
|
||||
continue;
|
||||
|
||||
// this optimization is to aggressive for most coarse-grain applications.
|
||||
// but we always want it for multiplexers driving write enable ports.
|
||||
if (do_fine || mem_wren_sigs.check_any(assign_map(cell->getPort(ID::Y))))
|
||||
opt_mux_bits(cell);
|
||||
if (do_fine || mem_wren_sigs.check_any(assign_map(cell->getPort(ID::Y)))) {
|
||||
if (cell->type == ID($demux)) {
|
||||
if (opt_demux_bits(cell))
|
||||
continue;
|
||||
} else {
|
||||
if (opt_mux_bits(cell))
|
||||
continue;
|
||||
}
|
||||
}
|
||||
|
||||
opt_mux(cell);
|
||||
if (cell->type.in(ID($mux), ID($pmux)))
|
||||
opt_pmux(cell);
|
||||
|
||||
if (cell->type == ID($bmux))
|
||||
opt_bmux(cell);
|
||||
|
||||
if (cell->type == ID($demux))
|
||||
opt_demux(cell);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
117
tests/opt/opt_reduce_bmux.ys
Normal file
117
tests/opt/opt_reduce_bmux.ys
Normal file
|
|
@ -0,0 +1,117 @@
|
|||
read_ilang << EOT
|
||||
|
||||
module \top
|
||||
wire width 12 input 0 \A
|
||||
wire width 2 input 1 \S
|
||||
wire width 6 output 2 \Y
|
||||
|
||||
cell $bmux $0
|
||||
parameter \WIDTH 6
|
||||
parameter \S_WIDTH 2
|
||||
connect \A { \A [11:10] \A [3:2] \A [10:9] \A [7] \A [7] \A [8] \A [2] \A [7:6] \A [5] \A [5] \A [3:2] \A [5:4] \A [1] \A [1] \A [3:0] }
|
||||
connect \S \S
|
||||
connect \Y \Y
|
||||
end
|
||||
end
|
||||
|
||||
EOT
|
||||
|
||||
equiv_opt -assert opt_reduce -fine
|
||||
opt_reduce -fine
|
||||
select -assert-count 1 t:$bmux r:WIDTH=4 %i
|
||||
|
||||
design -reset
|
||||
|
||||
read_ilang << EOT
|
||||
|
||||
module \top
|
||||
wire width 6 input 0 \A
|
||||
wire width 2 input 1 \S
|
||||
wire width 6 output 2 \Y
|
||||
|
||||
cell $bmux $0
|
||||
parameter \WIDTH 6
|
||||
parameter \S_WIDTH 2
|
||||
connect \A { \A [5:0] \A [5:0] \A [5:0] \A [5:0] }
|
||||
connect \S \S
|
||||
connect \Y \Y
|
||||
end
|
||||
end
|
||||
|
||||
EOT
|
||||
|
||||
equiv_opt -assert opt_reduce -fine
|
||||
opt_reduce -fine
|
||||
select -assert-count 0 t:$bmux
|
||||
|
||||
design -reset
|
||||
|
||||
read_ilang << EOT
|
||||
|
||||
module \top
|
||||
wire width 160 input 0 \A
|
||||
wire width 2 input 1 \S
|
||||
wire width 5 output 2 \Y
|
||||
|
||||
cell $bmux $0
|
||||
parameter \WIDTH 5
|
||||
parameter \S_WIDTH 5
|
||||
connect \A \A
|
||||
connect \S { \S [1] 1'1 \S [0] \S [1] 1'0 }
|
||||
connect \Y \Y
|
||||
end
|
||||
end
|
||||
|
||||
EOT
|
||||
|
||||
equiv_opt -assert opt_reduce -fine
|
||||
opt_reduce -fine
|
||||
select -assert-count 1 t:$bmux r:S_WIDTH=2 %i
|
||||
|
||||
design -reset
|
||||
|
||||
read_ilang << EOT
|
||||
|
||||
module \top
|
||||
wire width 10 input 0 \A
|
||||
wire input 1 \S
|
||||
wire width 5 output 2 \Y
|
||||
|
||||
cell $bmux $0
|
||||
parameter \WIDTH 5
|
||||
parameter \S_WIDTH 1
|
||||
connect \A \A
|
||||
connect \S \S
|
||||
connect \Y \Y
|
||||
end
|
||||
end
|
||||
|
||||
EOT
|
||||
|
||||
equiv_opt -assert opt_reduce -fine
|
||||
opt_reduce -fine
|
||||
select -assert-count 0 t:$bmux
|
||||
select -assert-count 1 t:$mux
|
||||
|
||||
design -reset
|
||||
|
||||
read_ilang << EOT
|
||||
|
||||
module \top
|
||||
wire width 5 input 0 \A
|
||||
wire width 5 output 1 \Y
|
||||
|
||||
cell $bmux $0
|
||||
parameter \WIDTH 5
|
||||
parameter \S_WIDTH 0
|
||||
connect \A \A
|
||||
connect \S { }
|
||||
connect \Y \Y
|
||||
end
|
||||
end
|
||||
|
||||
EOT
|
||||
|
||||
equiv_opt -assert opt_reduce -fine
|
||||
opt_reduce -fine
|
||||
select -assert-count 0 t:$bmux
|
||||
91
tests/opt/opt_reduce_demux.ys
Normal file
91
tests/opt/opt_reduce_demux.ys
Normal file
|
|
@ -0,0 +1,91 @@
|
|||
read_ilang << EOT
|
||||
|
||||
module \top
|
||||
wire width 4 input 0 \A
|
||||
wire width 2 input 1 \S
|
||||
wire width 24 output 2 \Y
|
||||
|
||||
cell $demux $0
|
||||
parameter \WIDTH 6
|
||||
parameter \S_WIDTH 2
|
||||
connect \A { \A [3] \A [1] 1'0 \A [2:0] }
|
||||
connect \S \S
|
||||
connect \Y \Y
|
||||
end
|
||||
end
|
||||
|
||||
EOT
|
||||
|
||||
equiv_opt -assert opt_reduce -fine
|
||||
opt_reduce -fine
|
||||
select -assert-count 1 t:$demux r:WIDTH=4 %i
|
||||
|
||||
design -reset
|
||||
|
||||
read_ilang << EOT
|
||||
|
||||
module \top
|
||||
wire width 2 input 1 \S
|
||||
wire width 24 output 2 \Y
|
||||
|
||||
cell $demux $0
|
||||
parameter \WIDTH 6
|
||||
parameter \S_WIDTH 2
|
||||
connect \A 6'000000
|
||||
connect \S \S
|
||||
connect \Y \Y
|
||||
end
|
||||
end
|
||||
|
||||
EOT
|
||||
|
||||
equiv_opt -assert opt_reduce -fine
|
||||
opt_reduce -fine
|
||||
select -assert-count 0 t:$demux
|
||||
|
||||
design -reset
|
||||
|
||||
read_ilang << EOT
|
||||
|
||||
module \top
|
||||
wire width 5 input 0 \A
|
||||
wire width 2 input 1 \S
|
||||
wire width 160 output 2 \Y
|
||||
|
||||
cell $demux $0
|
||||
parameter \WIDTH 5
|
||||
parameter \S_WIDTH 5
|
||||
connect \A \A
|
||||
connect \S { \S [0] \S [1] 1'1 \S [0] 1'0 }
|
||||
connect \Y \Y
|
||||
end
|
||||
end
|
||||
|
||||
EOT
|
||||
|
||||
equiv_opt -assert opt_reduce -fine
|
||||
opt_reduce -fine
|
||||
select -assert-count 1 t:$demux r:S_WIDTH=2 %i
|
||||
|
||||
design -reset
|
||||
|
||||
read_ilang << EOT
|
||||
|
||||
module \top
|
||||
wire width 5 input 0 \A
|
||||
wire width 20 output 2 \Y
|
||||
|
||||
cell $demux $0
|
||||
parameter \WIDTH 5
|
||||
parameter \S_WIDTH 2
|
||||
connect \A \A
|
||||
connect \S { 2'10 }
|
||||
connect \Y \Y
|
||||
end
|
||||
end
|
||||
|
||||
EOT
|
||||
|
||||
equiv_opt -assert opt_reduce -fine
|
||||
opt_reduce -fine
|
||||
select -assert-count 0 t:$demux
|
||||
Loading…
Add table
Add a link
Reference in a new issue