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verilog: fix case expression sign and width handling

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- The case expression and case item expressions are extended to the
  maximum width among them, and are only interpreted as signed if all of
  them are signed
- Add overall width and sign detection for AST_CASE
- Add sign argument to genWidthRTLIL helper
- Coverage for both const and non-const case statements
This commit is contained in:
Zachary Snow 2021-03-25 14:06:05 -04:00 • committed by Zachary Snow
parent 15f35d6754
commit 0795b3ec07
5 changed files with 157 additions and 12 deletions
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49
tests/simple/case_expr_const.v Normal file
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// Note: case_expr_{,non_}const.v should be modified in tandem to ensure both
// the constant and non-constant case evaluation logic is covered
module top(
// expected to output all 1s
output reg a, b, c, d, e, f, g, h
);
initial begin
case (2'b0)
1'b0: a = 1;
default: a = 0;
endcase
case (2'sb11)
2'sb01: b = 0;
1'sb1: b = 1;
endcase
case (2'sb11)
1'sb0: c = 0;
1'sb1: c = 1;
endcase
case (2'sb11)
1'b0: d = 0;
1'sb1: d = 0;
default: d = 1;
endcase
case (2'b11)
1'sb0: e = 0;
1'sb1: e = 0;
default: e = 1;
endcase
case (1'sb1)
1'sb0: f = 0;
2'sb11: f = 1;
default: f = 0;
endcase
case (1'sb1)
1'sb0: g = 0;
3'b0: g = 0;
2'sb11: g = 0;
default: g = 1;
endcase
case (1'sb1)
1'sb0: h = 0;
1'b1: h = 1;
3'b0: h = 0;
2'sb11: h = 0;
default: h = 0;
endcase
end
endmodule

59
tests/simple/case_expr_non_const.v Normal file
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// Note: case_expr_{,non_}const.v should be modified in tandem to ensure both
// the constant and non-constant case evaluation logic is covered
module top(
// expected to output all 1s
output reg a, b, c, d, e, f, g, h
);
reg x_1b0 = 1'b0;
reg x_1b1 = 1'b1;
reg signed x_1sb0 = 1'sb0;
reg signed x_1sb1 = 1'sb1;
reg [1:0] x_2b0 = 2'b0;
reg [1:0] x_2b11 = 2'b11;
reg signed [1:0] x_2sb01 = 2'sb01;
reg signed [1:0] x_2sb11 = 2'sb11;
reg [2:0] x_3b0 = 3'b0;
initial begin
case (x_2b0)
x_1b0: a = 1;
default: a = 0;
endcase
case (x_2sb11)
x_2sb01: b = 0;
x_1sb1: b = 1;
endcase
case (x_2sb11)
x_1sb0: c = 0;
x_1sb1: c = 1;
endcase
case (x_2sb11)
x_1b0: d = 0;
x_1sb1: d = 0;
default: d = 1;
endcase
case (x_2b11)
x_1sb0: e = 0;
x_1sb1: e = 0;
default: e = 1;
endcase
case (x_1sb1)
x_1sb0: f = 0;
x_2sb11: f = 1;
default: f = 0;
endcase
case (x_1sb1)
x_1sb0: g = 0;
x_3b0: g = 0;
x_2sb11: g = 0;
default: g = 1;
endcase
case (x_1sb1)
x_1sb0: h = 0;
x_1b1: h = 1;
x_3b0: h = 0;
x_2sb11: h = 0;
default: h = 0;
endcase
end
endmodule