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synth_ice40: always read abc9 model to understand port direction

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This commit is contained in:
Emil J. Tywoniak 2026-03-11 12:25:37 +01:00
parent 5b6b11dd44
commit 07628a4042
1 changed files with 1 additions and 1 deletions
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2
techlibs/ice40/synth_ice40.cc
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@ -380,6 +380,7 @@ struct SynthIce40Pass : public ScriptPass
run("techmap");
else {
run("ice40_wrapcarry");
run("read_verilog " + define + " -icells -lib -specify +/ice40/abc9_model.v");
run("techmap -map +/techmap.v -map +/ice40/arith_map.v");
}
run("opt -fast");
@ -416,7 +417,6 @@ struct SynthIce40Pass : public ScriptPass
}
if (!noabc) {
if (abc9) {
run("read_verilog " + define + " -icells -lib -specify +/ice40/abc9_model.v");
std::string abc9_opts;
std::string k = "synth_ice40.abc9.W";
if (active_design && active_design->scratchpad.count(k))