3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-23 22:33:41 +00:00

implementation for assignments working

This commit is contained in:
Stefan Biereigel 2019-05-23 10:16:41 +02:00
parent 9df04d7e75
commit 075a48d3fa
3 changed files with 83 additions and 14 deletions

View file

@ -51,6 +51,7 @@ namespace AST_INTERNAL {
std::map<std::string, AstNode*> current_scope;
const dict<RTLIL::SigBit, RTLIL::SigBit> *genRTLIL_subst_ptr = NULL;
RTLIL::SigSpec ignoreThisSignalsInInitial;
std::map<RTLIL::SigSpec, RTLIL::Cell*> wire_logic_map;
AstNode *current_always, *current_top_block, *current_block, *current_block_child;
AstModule *current_module;
bool current_always_clocked;
@ -940,6 +941,8 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast
log("--- END OF AST DUMP ---\n");
}
wire_logic_map = std::map<RTLIL::SigSpec, RTLIL::Cell*>();
if (!defer)
{
bool blackbox_module = flag_lib;