mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-03 21:09:12 +00:00
Code Activity

enable more primitives supported with nextpnr

Browse source
This commit is contained in:
Miodrag Milanovic 2023-08-25 11:45:25 +02:00
parent 3b9ebfa672
commit 0756285710
5 changed files with 135 additions and 18 deletions
Download patch file Download diff file Expand all files Collapse all files

36
techlibs/lattice/cells_bb_xo2.v
View file

@ -408,6 +408,17 @@ module FIFO8KB (...);
output FF;
endmodule
(* blackbox *)
module CLKDIVC (...);
parameter GSR = "DISABLED";
parameter DIV = "2.0";
input RST;
input CLKI;
input ALIGNWD;
output CDIV1;
output CDIVX;
endmodule
(* blackbox *)
module DCMA (...);
input CLK0;
@ -416,6 +427,21 @@ module DCMA (...);
output DCMOUT;
endmodule
(* blackbox *)
module ECLKSYNCA (...);
input ECLKI;
input STOP;
output ECLKO;
endmodule
(* blackbox *)
module ECLKBRIDGECS (...);
input CLK0;
input CLK1;
input SEL;
output ECSOUT;
endmodule
(* blackbox *)
module DCCA (...);
input CLKI;
@ -423,6 +449,11 @@ module DCCA (...);
output CLKO;
endmodule
(* blackbox *) (* keep *)
module START (...);
input STARTCLK;
endmodule
(* blackbox *)
module EHXPLLJ (...);
parameter CLKI_DIV = 1;
@ -533,3 +564,8 @@ module OSCH (...);
output SEDSTDBY;
endmodule
(* blackbox *) (* keep *)
module TSALL (...);
input TSALL;
endmodule

36
techlibs/lattice/cells_bb_xo3.v
View file

@ -408,6 +408,17 @@ module FIFO8KB (...);
output FF;
endmodule
(* blackbox *)
module CLKDIVC (...);
parameter GSR = "DISABLED";
parameter DIV = "2.0";
input RST;
input CLKI;
input ALIGNWD;
output CDIV1;
output CDIVX;
endmodule
(* blackbox *)
module DCMA (...);
input CLK0;
@ -416,6 +427,21 @@ module DCMA (...);
output DCMOUT;
endmodule
(* blackbox *)
module ECLKSYNCA (...);
input ECLKI;
input STOP;
output ECLKO;
endmodule
(* blackbox *)
module ECLKBRIDGECS (...);
input CLK0;
input CLK1;
input SEL;
output ECSOUT;
endmodule
(* blackbox *)
module DCCA (...);
input CLKI;
@ -423,6 +449,11 @@ module DCCA (...);
output CLKO;
endmodule
(* blackbox *) (* keep *)
module START (...);
input STARTCLK;
endmodule
(* blackbox *)
module EHXPLLJ (...);
parameter CLKI_DIV = 1;
@ -533,3 +564,8 @@ module OSCH (...);
output SEDSTDBY;
endmodule
(* blackbox *) (* keep *)
module TSALL (...);
input TSALL;
endmodule

36
techlibs/lattice/cells_bb_xo3d.v
View file

@ -408,6 +408,17 @@ module FIFO8KB (...);
output FF;
endmodule
(* blackbox *)
module CLKDIVC (...);
parameter GSR = "DISABLED";
parameter DIV = "2.0";
input RST;
input CLKI;
input ALIGNWD;
output CDIV1;
output CDIVX;
endmodule
(* blackbox *)
module DCMA (...);
input CLK0;
@ -416,6 +427,21 @@ module DCMA (...);
output DCMOUT;
endmodule
(* blackbox *)
module ECLKSYNCA (...);
input ECLKI;
input STOP;
output ECLKO;
endmodule
(* blackbox *)
module ECLKBRIDGECS (...);
input CLK0;
input CLK1;
input SEL;
output ECSOUT;
endmodule
(* blackbox *)
module DCCA (...);
input CLKI;
@ -423,6 +449,11 @@ module DCCA (...);
output CLKO;
endmodule
(* blackbox *) (* keep *)
module START (...);
input STARTCLK;
endmodule
(* blackbox *)
module EHXPLLJ (...);
parameter CLKI_DIV = 1;
@ -534,3 +565,8 @@ module OSCJ (...);
output OSCESB;
endmodule
(* blackbox *) (* keep *)
module TSALL (...);
input TSALL;
endmodule

36
techlibs/lattice/cells_xtra.py
View file

@ -315,13 +315,13 @@ devices = [
Cell("PDPW8KC"),
Cell("SP8KC"),
Cell("FIFO8KB"),
#Cell("CLKDIVC"),
Cell("CLKDIVC"),
Cell("DCMA"),
#Cell("ECLKSYNCA"),
#Cell("ECLKBRIDGECS"),
Cell("ECLKSYNCA"),
Cell("ECLKBRIDGECS"),
Cell("DCCA"),
#Cell("JTAGF"),
#Cell("START"),
#Cell("JTAGF", True, port_attrs={'TCK': ['iopad_external_pin'], 'TMS': ['iopad_external_pin'], 'TDO': ['iopad_external_pin'], 'TDI': ['iopad_external_pin']}),
Cell("START", True),
#Cell("SEDFA"),
#Cell("SEDFB"),
#Cell("IDDRXE"),
@ -351,7 +351,7 @@ devices = [
#Cell("PLLREFCS"),
Cell("OSCH"),
#Cell("EFB"),
#Cell("TSALL"),
Cell("TSALL", True),
]),
("cells_bb_xo3.v", "machxo3lf", [
#Cell("AGEB2"),
@ -495,13 +495,13 @@ devices = [
Cell("PDPW8KC"),
Cell("SP8KC"),
Cell("FIFO8KB"),
#Cell("CLKDIVC"),
Cell("CLKDIVC"),
Cell("DCMA"),
#Cell("ECLKSYNCA"),
#Cell("ECLKBRIDGECS"),
Cell("ECLKSYNCA"),
Cell("ECLKBRIDGECS"),
Cell("DCCA"),
#Cell("JTAGF"),
#Cell("START"),
#Cell("JTAGF", True, port_attrs={'TCK': ['iopad_external_pin'], 'TMS': ['iopad_external_pin'], 'TDO': ['iopad_external_pin'], 'TDI': ['iopad_external_pin']}),
Cell("START", True),
#Cell("SEDFA"),
#Cell("SEDFB"),
#Cell("IDDRXE"),
@ -527,7 +527,7 @@ devices = [
#Cell("PLLREFCS"),
Cell("OSCH"),
#Cell("EFB"),
#Cell("TSALL"),
Cell("TSALL", True),
]),
("cells_bb_xo3d.v", "machxo3d", [
#Cell("AGEB2"),
@ -672,13 +672,13 @@ devices = [
Cell("PDPW8KC"),
Cell("SP8KC"),
Cell("FIFO8KB"),
#Cell("CLKDIVC"),
Cell("CLKDIVC"),
Cell("DCMA"),
#Cell("ECLKSYNCA"),
#Cell("ECLKBRIDGECS"),
Cell("ECLKSYNCA"),
Cell("ECLKBRIDGECS"),
Cell("DCCA"),
#Cell("JTAGF"),
#Cell("START"),
#Cell("JTAGF", True, port_attrs={'TCK': ['iopad_external_pin'], 'TMS': ['iopad_external_pin'], 'TDO': ['iopad_external_pin'], 'TDI': ['iopad_external_pin']}),
Cell("START", True),
#Cell("SEDFA"),
#Cell("SEDFB"),
#Cell("IDDRXE"),
@ -704,7 +704,7 @@ devices = [
#Cell("PLLREFCS"),
Cell("OSCJ"),
#Cell("EFBB"),
#Cell("TSALL"),
Cell("TSALL", True),
#Cell("ESBA"),
#Cell("BCSLEWRATEA"),
])

9
techlibs/lattice/common_sim.vh
View file

@ -394,6 +394,15 @@ module TRELLIS_COMB(
endmodule
// Constants
module VLO(output Z);
assign Z = 1'b0;
endmodule
module VHI(output Z);
assign Z = 1'b1;
endmodule
`ifndef NO_INCLUDES
`include "cells_ff.vh"