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Merge remote-tracking branch 'origin/eddie/fix_carry_wrapper' into xaig_arrival

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Eddie Hung 2019-08-28 17:29:25 -07:00
commit 070f3ac561
2 changed files with 48 additions and 1 deletions
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2
techlibs/ice40/cells_sim.v
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@ -153,7 +153,7 @@ module \$__ICE40_CARRY_WRAPPER (
input A, B, input A, B,
(* abc_carry *) (* abc_carry *)
input CI, input CI,
input I0, I3, input I0, I3
); );
parameter LUT = 0; parameter LUT = 0;
SB_CARRY carry ( SB_CARRY carry (

47
techlibs/ice40/ice40_opt.cc
View file

@ -83,6 +83,53 @@ static void run_ice40_opts(Module *module)
} }
continue; continue;
} }
if (cell->type == "$__ICE40_CARRY_WRAPPER")
{
SigSpec non_const_inputs, replacement_output;
int count_zeros = 0, count_ones = 0;
SigBit inbit[3] = {
cell->getPort("\\A"),
cell->getPort("\\B"),
cell->getPort("\\CI")
};
for (int i = 0; i < 3; i++)
if (inbit[i].wire == nullptr) {
if (inbit[i] == State::S1)
count_ones++;
else
count_zeros++;
} else
non_const_inputs.append(inbit[i]);
if (count_zeros >= 2)
replacement_output = State::S0;
else if (count_ones >= 2)
replacement_output = State::S1;
else if (GetSize(non_const_inputs) == 1)
replacement_output = non_const_inputs;
if (GetSize(replacement_output)) {
optimized_co.insert(sigmap(cell->getPort("\\CO")[0]));
module->connect(cell->getPort("\\CO")[0], replacement_output);
module->design->scratchpad_set_bool("opt.did_something", true);
log("Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n",
log_id(module), log_id(cell), log_signal(replacement_output));
cell->type = "$lut";
cell->setPort("\\A", { cell->getPort("\\I0"), inbit[0], inbit[1], cell->getPort("\\I3") });
cell->setPort("\\Y", cell->getPort("\\O"));
cell->unsetPort("\\B");
cell->unsetPort("\\CI");
cell->unsetPort("\\I0");
cell->unsetPort("\\I3");
cell->unsetPort("\\CO");
cell->unsetPort("\\O");
cell->setParam("\\LUT", RTLIL::Const::from_string("0110100110010110"));
cell->setParam("\\WIDTH", 4);
}
continue;
}
} }
for (auto cell : sb_lut_cells) for (auto cell : sb_lut_cells)