mirror of
https://github.com/YosysHQ/yosys
synced 2025-11-03 21:09:12 +00:00
Working
This commit is contained in:
Eddie Hung
parent
e7ef7fa443
commit
06f8f2654a
3 changed files with 470 additions and 310 deletions
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@ -26,7 +26,9 @@ PRIVATE_NAMESPACE_BEGIN
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struct ShregmapTech
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{
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virtual ~ShregmapTech() { }
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virtual bool analyze(vector<int> &taps) = 0;
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virtual void init(const Module * /*module*/, const SigMap &/*sigmap*/) {}
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virtual void non_chain_user(const SigBit &/*bit*/, const Cell* /*cell*/, IdString /*port*/) {}
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virtual bool analyze(vector<int> &taps, const vector<SigBit> &qbits) = 0;
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virtual bool fixup(Cell *cell, dict<int, SigBit> &taps) = 0;
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};
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@ -54,7 +56,7 @@ struct ShregmapOptions
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struct ShregmapTechGreenpak4 : ShregmapTech
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{
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bool analyze(vector<int> &taps)
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bool analyze(vector<int> &taps, const vector<SigBit> &/*qbits*/)
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{
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if (GetSize(taps) > 2 && taps[0] == 0 && taps[2] < 17) {
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taps.clear();
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@ -91,302 +93,423 @@ struct ShregmapTechGreenpak4 : ShregmapTech
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}
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};
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struct ShregmapTechXilinx7 : ShregmapTech
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{
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dict<SigBit, Cell*> sigbit_to_shiftx;
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const ShregmapOptions &opts;
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ShregmapTechXilinx7(const ShregmapOptions &opts) : opts(opts) {}
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virtual void init(const Module* module, const SigMap &sigmap) override
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{
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for (auto i : module->cells_) {
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auto cell = i.second;
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if (cell->type != "$shiftx") continue;
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if (cell->getParam("\\Y_WIDTH") != 1) continue;
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for (auto bit : sigmap(cell->getPort("\\A")))
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sigbit_to_shiftx[bit] = cell;
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}
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}
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virtual void non_chain_user(const SigBit &bit, const Cell *cell, IdString port) override
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{
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auto it = sigbit_to_shiftx.find(bit);
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if (it == sigbit_to_shiftx.end())
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return;
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if (cell->type == "$shiftx" && port == "\\A")
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return;
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it->second = nullptr;
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}
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virtual bool analyze(vector<int> &taps, const vector<SigBit> &qbits) override
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{
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if (GetSize(taps) == 1)
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return taps[0] >= opts.minlen-1;
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if (taps.back() < opts.minlen-1)
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return false;
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Cell *shiftx = nullptr;
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int offset = 0;
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for (int i = 0; i < GetSize(taps); ++i) {
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// Check taps are sequential
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if (i != taps[i])
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return false;
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// Check taps are not connected to a shift register,
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// or sequential to the same shift register
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auto it = sigbit_to_shiftx.find(qbits[i]);
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if (i == 0) {
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if (it != sigbit_to_shiftx.end()) {
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shiftx = it->second;
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// NULL indicates there are non-shiftx users
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if (shiftx == nullptr)
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return false;
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offset = qbits[i].offset;
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}
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}
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else {
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if (it == sigbit_to_shiftx.end()) {
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if (shiftx != nullptr)
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return false;
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}
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else {
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if (shiftx != it->second)
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return false;
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if (qbits[i].offset != offset + i)
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return false;
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}
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}
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}
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return true;
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}
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virtual bool fixup(Cell *cell, dict<int, SigBit> &taps) override
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{
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const auto &tap = *taps.begin();
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auto bit = tap.second;
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auto it = sigbit_to_shiftx.find(bit);
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if (it == sigbit_to_shiftx.end())
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return true;
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Cell* shiftx = it->second;
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auto module = cell->module;
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auto cell_q = cell->getPort("\\Q").as_bit();
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auto shiftx_a = shiftx->getPort("\\A").bits();
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int offset = 0;
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for (auto bit : shiftx_a) {
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if (bit == cell_q)
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break;
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++offset;
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}
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offset -= taps.size() - 1;
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log_assert(offset >= 0);
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for (size_t i = offset; i < offset + taps.size(); ++i)
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shiftx_a[i] = cell_q;
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// FIXME: Hack to ensure that $shiftx gets optimised away
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// Without this, Yosys will refuse to optimise away a $shiftx
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// where \\A 's width is not perfectly \\B_WIDTH ** 2
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auto shiftx_bwidth = shiftx->getParam("\\B_WIDTH").as_int();
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shiftx_a.resize(1 << shiftx_bwidth, shiftx_a.back());
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shiftx->setPort("\\A", shiftx_a);
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shiftx->setParam("\\A_WIDTH", shiftx_a.size());
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auto length = module->addWire(NEW_ID, ceil(log2(taps.size())));
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module->addSub(NEW_ID, shiftx->getPort("\\B"), RTLIL::Const(offset, ceil(log2(offset))), length);
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cell->setPort("\\L", length);
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return true;
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}
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};
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struct ShregmapWorker
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{
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Module *module;
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SigMap sigmap;
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Module *module;
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SigMap sigmap;
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const ShregmapOptions &opts;
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int dff_count, shreg_count;
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const ShregmapOptions &opts;
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int dff_count, shreg_count;
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pool<Cell*> remove_cells;
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pool<SigBit> remove_init;
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pool<Cell*> remove_cells;
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pool<SigBit> remove_init;
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dict<SigBit, bool> sigbit_init;
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dict<SigBit, Cell*> sigbit_chain_next;
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dict<SigBit, Cell*> sigbit_chain_prev;
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pool<SigBit> sigbit_with_non_chain_users;
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pool<Cell*> chain_start_cells;
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dict<SigBit, bool> sigbit_init;
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dict<SigBit, Cell*> sigbit_chain_next;
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dict<SigBit, Cell*> sigbit_chain_prev;
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pool<SigBit> sigbit_with_non_chain_users;
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pool<Cell*> chain_start_cells;
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void make_sigbit_chain_next_prev()
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void make_sigbit_chain_next_prev()
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{
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for (auto wire : module->wires())
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{
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for (auto wire : module->wires())
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{
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if (wire->port_output || wire->get_bool_attribute("\\keep")) {
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for (auto bit : sigmap(wire))
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sigbit_with_non_chain_users.insert(bit);
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}
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if (wire->port_output || wire->get_bool_attribute("\\keep")) {
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for (auto bit : sigmap(wire))
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sigbit_with_non_chain_users.insert(bit);
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}
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if (wire->attributes.count("\\init")) {
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SigSpec initsig = sigmap(wire);
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Const initval = wire->attributes.at("\\init");
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for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++)
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if (initval[i] == State::S0 && !opts.zinit)
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sigbit_init[initsig[i]] = false;
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else if (initval[i] == State::S1)
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sigbit_init[initsig[i]] = true;
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}
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}
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for (auto cell : module->cells())
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{
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if (opts.ffcells.count(cell->type) && !cell->get_bool_attribute("\\keep"))
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{
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IdString d_port = opts.ffcells.at(cell->type).first;
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IdString q_port = opts.ffcells.at(cell->type).second;
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SigBit d_bit = sigmap(cell->getPort(d_port).as_bit());
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SigBit q_bit = sigmap(cell->getPort(q_port).as_bit());
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if (opts.init || sigbit_init.count(q_bit) == 0)
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{
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if (sigbit_chain_next.count(d_bit)) {
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sigbit_with_non_chain_users.insert(d_bit);
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} else
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sigbit_chain_next[d_bit] = cell;
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sigbit_chain_prev[q_bit] = cell;
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continue;
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}
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}
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for (auto conn : cell->connections())
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if (cell->input(conn.first))
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for (auto bit : sigmap(conn.second))
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sigbit_with_non_chain_users.insert(bit);
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}
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if (wire->attributes.count("\\init")) {
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SigSpec initsig = sigmap(wire);
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Const initval = wire->attributes.at("\\init");
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for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++)
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if (initval[i] == State::S0 && !opts.zinit)
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sigbit_init[initsig[i]] = false;
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else if (initval[i] == State::S1)
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sigbit_init[initsig[i]] = true;
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}
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}
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void find_chain_start_cells()
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for (auto cell : module->cells())
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{
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for (auto it : sigbit_chain_next)
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if (opts.ffcells.count(cell->type) && !cell->get_bool_attribute("\\keep"))
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{
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IdString d_port = opts.ffcells.at(cell->type).first;
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IdString q_port = opts.ffcells.at(cell->type).second;
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SigBit d_bit = sigmap(cell->getPort(d_port).as_bit());
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SigBit q_bit = sigmap(cell->getPort(q_port).as_bit());
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if (opts.init || sigbit_init.count(q_bit) == 0)
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{
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if (opts.tech == nullptr && sigbit_with_non_chain_users.count(it.first))
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goto start_cell;
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if (sigbit_chain_next.count(d_bit)) {
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sigbit_with_non_chain_users.insert(d_bit);
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} else
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sigbit_chain_next[d_bit] = cell;
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if (sigbit_chain_prev.count(it.first) != 0)
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{
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Cell *c1 = sigbit_chain_prev.at(it.first);
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Cell *c2 = it.second;
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if (c1->type != c2->type)
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goto start_cell;
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if (c1->parameters != c2->parameters)
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goto start_cell;
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IdString d_port = opts.ffcells.at(c1->type).first;
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IdString q_port = opts.ffcells.at(c1->type).second;
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auto c1_conn = c1->connections();
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auto c2_conn = c1->connections();
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c1_conn.erase(d_port);
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c1_conn.erase(q_port);
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c2_conn.erase(d_port);
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c2_conn.erase(q_port);
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if (c1_conn != c2_conn)
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goto start_cell;
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continue;
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}
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start_cell:
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chain_start_cells.insert(it.second);
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sigbit_chain_prev[q_bit] = cell;
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continue;
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}
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}
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for (auto conn : cell->connections())
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if (cell->input(conn.first))
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for (auto bit : sigmap(conn.second)) {
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sigbit_with_non_chain_users.insert(bit);
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if (opts.tech) opts.tech->non_chain_user(bit, cell, conn.first);
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}
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}
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}
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void find_chain_start_cells()
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{
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for (auto it : sigbit_chain_next)
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{
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if (opts.tech == nullptr && sigbit_with_non_chain_users.count(it.first))
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goto start_cell;
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if (sigbit_chain_prev.count(it.first) != 0)
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{
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Cell *c1 = sigbit_chain_prev.at(it.first);
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Cell *c2 = it.second;
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if (c1->type != c2->type)
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goto start_cell;
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if (c1->parameters != c2->parameters)
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goto start_cell;
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IdString d_port = opts.ffcells.at(c1->type).first;
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IdString q_port = opts.ffcells.at(c1->type).second;
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auto c1_conn = c1->connections();
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auto c2_conn = c1->connections();
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c1_conn.erase(d_port);
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c1_conn.erase(q_port);
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c2_conn.erase(d_port);
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c2_conn.erase(q_port);
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if (c1_conn != c2_conn)
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goto start_cell;
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continue;
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}
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start_cell:
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chain_start_cells.insert(it.second);
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}
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}
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vector<Cell*> create_chain(Cell *start_cell)
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{
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vector<Cell*> chain;
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Cell *c = start_cell;
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while (c != nullptr)
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{
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chain.push_back(c);
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IdString q_port = opts.ffcells.at(c->type).second;
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SigBit q_bit = sigmap(c->getPort(q_port).as_bit());
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if (sigbit_chain_next.count(q_bit) == 0)
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break;
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c = sigbit_chain_next.at(q_bit);
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if (chain_start_cells.count(c) != 0)
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break;
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}
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vector<Cell*> create_chain(Cell *start_cell)
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{
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vector<Cell*> chain;
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return chain;
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}
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Cell *c = start_cell;
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while (c != nullptr)
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void process_chain(vector<Cell*> &chain)
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{
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if (GetSize(chain) < opts.keep_before + opts.minlen + opts.keep_after)
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return;
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int cursor = opts.keep_before;
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while (cursor < GetSize(chain) - opts.keep_after)
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{
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int depth = GetSize(chain) - opts.keep_after - cursor;
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if (opts.maxlen > 0)
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depth = std::min(opts.maxlen, depth);
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Cell *first_cell = chain[cursor];
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IdString q_port = opts.ffcells.at(first_cell->type).second;
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dict<int, SigBit> taps_dict;
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if (opts.tech)
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{
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vector<SigBit> qbits;
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vector<int> taps;
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for (int i = 0; i < depth; i++)
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{
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chain.push_back(c);
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Cell *cell = chain[cursor+i];
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auto qbit = sigmap(cell->getPort(q_port));
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qbits.push_back(qbit);
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IdString q_port = opts.ffcells.at(c->type).second;
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SigBit q_bit = sigmap(c->getPort(q_port).as_bit());
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if (sigbit_chain_next.count(q_bit) == 0)
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break;
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c = sigbit_chain_next.at(q_bit);
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if (chain_start_cells.count(c) != 0)
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break;
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if (sigbit_with_non_chain_users.count(qbit))
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taps.push_back(i);
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}
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return chain;
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}
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void process_chain(vector<Cell*> &chain)
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{
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if (GetSize(chain) < opts.keep_before + opts.minlen + opts.keep_after)
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return;
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int cursor = opts.keep_before;
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while (cursor < GetSize(chain) - opts.keep_after)
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while (depth > 0)
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{
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int depth = GetSize(chain) - opts.keep_after - cursor;
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if (taps.empty() || taps.back() < depth-1)
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taps.push_back(depth-1);
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if (opts.maxlen > 0)
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depth = std::min(opts.maxlen, depth);
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if (opts.tech->analyze(taps, qbits))
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break;
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Cell *first_cell = chain[cursor];
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IdString q_port = opts.ffcells.at(first_cell->type).second;
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dict<int, SigBit> taps_dict;
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if (opts.tech)
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{
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vector<SigBit> qbits;
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vector<int> taps;
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for (int i = 0; i < depth; i++)
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{
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Cell *cell = chain[cursor+i];
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auto qbit = sigmap(cell->getPort(q_port));
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qbits.push_back(qbit);
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if (sigbit_with_non_chain_users.count(qbit))
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taps.push_back(i);
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}
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while (depth > 0)
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{
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if (taps.empty() || taps.back() < depth-1)
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taps.push_back(depth-1);
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if (opts.tech->analyze(taps))
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break;
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taps.pop_back();
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depth--;
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}
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depth = 0;
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for (auto tap : taps) {
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taps_dict[tap] = qbits.at(tap);
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log_assert(depth < tap+1);
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depth = tap+1;
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}
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}
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if (depth < 2) {
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cursor++;
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continue;
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}
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Cell *last_cell = chain[cursor+depth-1];
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log("Converting %s.%s ... %s.%s to a shift register with depth %d.\n",
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log_id(module), log_id(first_cell), log_id(module), log_id(last_cell), depth);
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dff_count += depth;
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shreg_count += 1;
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|
||||
string shreg_cell_type_str = "$__SHREG";
|
||||
if (opts.params) {
|
||||
shreg_cell_type_str += "_";
|
||||
} else {
|
||||
if (first_cell->type[1] != '_')
|
||||
shreg_cell_type_str += "_";
|
||||
shreg_cell_type_str += first_cell->type.substr(1);
|
||||
}
|
||||
|
||||
if (opts.init) {
|
||||
vector<State> initval;
|
||||
for (int i = depth-1; i >= 0; i--) {
|
||||
SigBit bit = sigmap(chain[cursor+i]->getPort(q_port).as_bit());
|
||||
if (sigbit_init.count(bit) == 0)
|
||||
initval.push_back(State::Sx);
|
||||
else if (sigbit_init.at(bit))
|
||||
initval.push_back(State::S1);
|
||||
else
|
||||
initval.push_back(State::S0);
|
||||
remove_init.insert(bit);
|
||||
}
|
||||
first_cell->setParam("\\INIT", initval);
|
||||
}
|
||||
|
||||
if (opts.zinit)
|
||||
for (int i = depth-1; i >= 0; i--) {
|
||||
SigBit bit = sigmap(chain[cursor+i]->getPort(q_port).as_bit());
|
||||
remove_init.insert(bit);
|
||||
}
|
||||
|
||||
if (opts.params)
|
||||
{
|
||||
int param_clkpol = -1;
|
||||
int param_enpol = 2;
|
||||
|
||||
if (first_cell->type == "$_DFF_N_") param_clkpol = 0;
|
||||
if (first_cell->type == "$_DFF_P_") param_clkpol = 1;
|
||||
|
||||
if (first_cell->type == "$_DFFE_NN_") param_clkpol = 0, param_enpol = 0;
|
||||
if (first_cell->type == "$_DFFE_NP_") param_clkpol = 0, param_enpol = 1;
|
||||
if (first_cell->type == "$_DFFE_PN_") param_clkpol = 1, param_enpol = 0;
|
||||
if (first_cell->type == "$_DFFE_PP_") param_clkpol = 1, param_enpol = 1;
|
||||
|
||||
log_assert(param_clkpol >= 0);
|
||||
first_cell->setParam("\\CLKPOL", param_clkpol);
|
||||
if (opts.ffe) first_cell->setParam("\\ENPOL", param_enpol);
|
||||
}
|
||||
|
||||
first_cell->type = shreg_cell_type_str;
|
||||
first_cell->setPort(q_port, last_cell->getPort(q_port));
|
||||
first_cell->setParam("\\DEPTH", depth);
|
||||
|
||||
if (opts.tech != nullptr && !opts.tech->fixup(first_cell, taps_dict))
|
||||
remove_cells.insert(first_cell);
|
||||
|
||||
for (int i = 1; i < depth; i++)
|
||||
remove_cells.insert(chain[cursor+i]);
|
||||
cursor += depth;
|
||||
taps.pop_back();
|
||||
depth--;
|
||||
}
|
||||
}
|
||||
|
||||
void cleanup()
|
||||
depth = 0;
|
||||
for (auto tap : taps) {
|
||||
taps_dict[tap] = qbits.at(tap);
|
||||
log_assert(depth < tap+1);
|
||||
depth = tap+1;
|
||||
}
|
||||
}
|
||||
|
||||
if (depth < 2) {
|
||||
cursor++;
|
||||
continue;
|
||||
}
|
||||
|
||||
Cell *last_cell = chain[cursor+depth-1];
|
||||
|
||||
log("Converting %s.%s ... %s.%s to a shift register with depth %d.\n",
|
||||
log_id(module), log_id(first_cell), log_id(module), log_id(last_cell), depth);
|
||||
|
||||
dff_count += depth;
|
||||
shreg_count += 1;
|
||||
|
||||
string shreg_cell_type_str = "$__SHREG";
|
||||
if (opts.params) {
|
||||
shreg_cell_type_str += "_";
|
||||
} else {
|
||||
if (first_cell->type[1] != '_')
|
||||
shreg_cell_type_str += "_";
|
||||
shreg_cell_type_str += first_cell->type.substr(1);
|
||||
}
|
||||
|
||||
if (opts.init) {
|
||||
vector<State> initval;
|
||||
for (int i = depth-1; i >= 0; i--) {
|
||||
SigBit bit = sigmap(chain[cursor+i]->getPort(q_port).as_bit());
|
||||
if (sigbit_init.count(bit) == 0)
|
||||
initval.push_back(State::Sx);
|
||||
else if (sigbit_init.at(bit))
|
||||
initval.push_back(State::S1);
|
||||
else
|
||||
initval.push_back(State::S0);
|
||||
remove_init.insert(bit);
|
||||
}
|
||||
first_cell->setParam("\\INIT", initval);
|
||||
}
|
||||
|
||||
if (opts.zinit)
|
||||
for (int i = depth-1; i >= 0; i--) {
|
||||
SigBit bit = sigmap(chain[cursor+i]->getPort(q_port).as_bit());
|
||||
remove_init.insert(bit);
|
||||
}
|
||||
|
||||
if (opts.params)
|
||||
{
|
||||
int param_clkpol = -1;
|
||||
int param_enpol = 2;
|
||||
|
||||
if (first_cell->type == "$_DFF_N_") param_clkpol = 0;
|
||||
if (first_cell->type == "$_DFF_P_") param_clkpol = 1;
|
||||
|
||||
if (first_cell->type == "$_DFFE_NN_") param_clkpol = 0, param_enpol = 0;
|
||||
if (first_cell->type == "$_DFFE_NP_") param_clkpol = 0, param_enpol = 1;
|
||||
if (first_cell->type == "$_DFFE_PN_") param_clkpol = 1, param_enpol = 0;
|
||||
if (first_cell->type == "$_DFFE_PP_") param_clkpol = 1, param_enpol = 1;
|
||||
|
||||
log_assert(param_clkpol >= 0);
|
||||
first_cell->setParam("\\CLKPOL", param_clkpol);
|
||||
if (opts.ffe) first_cell->setParam("\\ENPOL", param_enpol);
|
||||
}
|
||||
|
||||
first_cell->type = shreg_cell_type_str;
|
||||
first_cell->setPort(q_port, last_cell->getPort(q_port));
|
||||
if (!first_cell->hasPort("\\L"))
|
||||
first_cell->setPort("\\L", depth-1);
|
||||
first_cell->setParam("\\DEPTH", depth);
|
||||
|
||||
if (opts.tech != nullptr && !opts.tech->fixup(first_cell, taps_dict))
|
||||
remove_cells.insert(first_cell);
|
||||
|
||||
for (int i = 1; i < depth; i++)
|
||||
remove_cells.insert(chain[cursor+i]);
|
||||
cursor += depth;
|
||||
}
|
||||
}
|
||||
|
||||
void cleanup()
|
||||
{
|
||||
for (auto cell : remove_cells)
|
||||
module->remove(cell);
|
||||
|
||||
for (auto wire : module->wires())
|
||||
{
|
||||
for (auto cell : remove_cells)
|
||||
module->remove(cell);
|
||||
if (wire->attributes.count("\\init") == 0)
|
||||
continue;
|
||||
|
||||
for (auto wire : module->wires())
|
||||
{
|
||||
if (wire->attributes.count("\\init") == 0)
|
||||
continue;
|
||||
SigSpec initsig = sigmap(wire);
|
||||
Const &initval = wire->attributes.at("\\init");
|
||||
|
||||
SigSpec initsig = sigmap(wire);
|
||||
Const &initval = wire->attributes.at("\\init");
|
||||
for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++)
|
||||
if (remove_init.count(initsig[i]))
|
||||
initval[i] = State::Sx;
|
||||
|
||||
for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++)
|
||||
if (remove_init.count(initsig[i]))
|
||||
initval[i] = State::Sx;
|
||||
|
||||
if (SigSpec(initval).is_fully_undef())
|
||||
wire->attributes.erase("\\init");
|
||||
}
|
||||
|
||||
remove_cells.clear();
|
||||
sigbit_chain_next.clear();
|
||||
sigbit_chain_prev.clear();
|
||||
chain_start_cells.clear();
|
||||
if (SigSpec(initval).is_fully_undef())
|
||||
wire->attributes.erase("\\init");
|
||||
}
|
||||
|
||||
ShregmapWorker(Module *module, const ShregmapOptions &opts) :
|
||||
module(module), sigmap(module), opts(opts), dff_count(0), shreg_count(0)
|
||||
{
|
||||
make_sigbit_chain_next_prev();
|
||||
find_chain_start_cells();
|
||||
remove_cells.clear();
|
||||
sigbit_chain_next.clear();
|
||||
sigbit_chain_prev.clear();
|
||||
chain_start_cells.clear();
|
||||
}
|
||||
|
||||
for (auto c : chain_start_cells) {
|
||||
vector<Cell*> chain = create_chain(c);
|
||||
process_chain(chain);
|
||||
}
|
||||
ShregmapWorker(Module *module, const ShregmapOptions &opts) :
|
||||
module(module), sigmap(module), opts(opts), dff_count(0), shreg_count(0)
|
||||
{
|
||||
if (opts.tech)
|
||||
opts.tech->init(module, sigmap);
|
||||
|
||||
cleanup();
|
||||
make_sigbit_chain_next_prev();
|
||||
find_chain_start_cells();
|
||||
|
||||
for (auto c : chain_start_cells) {
|
||||
vector<Cell*> chain = create_chain(c);
|
||||
process_chain(chain);
|
||||
}
|
||||
|
||||
cleanup();
|
||||
}
|
||||
};
|
||||
|
||||
struct ShregmapPass : public Pass {
|
||||
|
|
@ -501,6 +624,12 @@ struct ShregmapPass : public Pass {
|
|||
clkpol = "pos";
|
||||
opts.zinit = true;
|
||||
opts.tech = new ShregmapTechGreenpak4;
|
||||
}
|
||||
else if (tech == "xilinx") {
|
||||
opts.init = true;
|
||||
opts.params = true;
|
||||
enpol = "any_or_none";
|
||||
opts.tech = new ShregmapTechXilinx7(opts);
|
||||
} else {
|
||||
argidx--;
|
||||
break;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue