add options for edif flavors

*to force renames on wide ports
*to choose array delimiters
*to choose up or downwards indices

Makefile

@@ -7,9 +7,9 @@ CONFIG := clang
 # CONFIG := msys2
 
 # features (the more the better)
-ENABLE_TCL := 1
+ENABLE_TCL := 0
-ENABLE_ABC := 1
+ENABLE_ABC := 0
-ENABLE_PLUGINS := 1
+ENABLE_PLUGINS := 0
 ENABLE_READLINE := 1
 ENABLE_VERIFIC := 0
 ENABLE_COVER := 1

backends/edif/edif.cc

@@ -31,8 +31,12 @@ USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
 #define EDIF_DEF(_id) edif_names(RTLIL::unescape_id(_id), true).c_str()
+#define EDIF_DEFR(_id, _ren, _del, _bd) edif_names(RTLIL::unescape_id(_id), true, _ren, _del, _bd).c_str()
 #define EDIF_REF(_id) edif_names(RTLIL::unescape_id(_id), false).c_str()
 
+static char const edf_defdel[2] = {'[',']'};
+static int const edf_defbd[2] = {0,1};
+
 namespace
 {
 	struct EdifNames
@@ -43,10 +47,12 @@ namespace
 
 		EdifNames() : counter(1) { }
 
-		std::string operator()(std::string id, bool define)
+		std::string operator()(std::string id, bool define, bool always_rename = false, char const delim[2] = edf_defdel, int const bounds[2] = edf_defbd)
 		{
 			if (define) {
 				std::string new_id = operator()(id, false);
+				if (always_rename)
+					return stringf("(rename %s \"%s%c%d:%d%c\")", new_id.c_str(), id.c_str(), delim[0], bounds[0], bounds[1], delim[1]);
 				return new_id != id ? stringf("(rename %s \"%s\")", new_id.c_str(), id.c_str()) : id;
 			}
 
@@ -105,6 +111,25 @@ struct EdifBackend : public Backend {
 		log("        if the design contains constant nets. use \"hilomap\" to map to custom\n");
 		log("        constant drivers first)\n");
 		log("\n");
+		log("    -pidx {up|down}\n");
+		log("        adds rename clauses to all module ports to line up signal and member indices.\n");
+		log("        if it is up, a 24 bit port will be renamed as follows:\n");
+		log("                (rename mcu_addr \"mcu_addr[0:23]\")\n");
+		log("        if it is down, it will be:\n");
+		log("                (rename mcu_addr \"mcu_addr[23:0]\")\n");
+		log("\n");
+		log("    -parray {par|bra|ang}\n");
+		log("        sets the delimiting character for module port rename clauses.\n");
+		log("        if it is par, The example from above will be:\n");
+		log("                (rename mcu_addr \"mcu_addr(0:23)\")\n");
+		log("        if it is ang, The example from above will be:\n");
+		log("                (rename mcu_addr \"mcu_addr<0:23>\")\n");
+		log("        otherwise:\n");
+		log("                (rename mcu_addr \"mcu_addr[0:23]\")\n");
+		log("\n");
+		log("    If neither -parray nor -pidx are given, there will be no port rename clauses.");
+		log("    If only one is given, -parray will default to bra and -pidx to up.");
+		log("\n");
 		log("Unfortunately there are different \"flavors\" of the EDIF file format. This\n");
 		log("command generates EDIF files for the Xilinx place&route tools. It might be\n");
 		log("necessary to make small modifications to this command when a different tool\n");
@@ -114,8 +139,10 @@ struct EdifBackend : public Backend {
 	virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
 	{
 		log_header(design, "Executing EDIF backend.\n");
-
 		std::string top_module_name;
+		bool always_rename = false;
+		char delim[2] = {'[',']'};
+		int bounds[2] = {0,1};
 		std::map<RTLIL::IdString, std::map<RTLIL::IdString, int>> lib_cell_ports;
 		bool nogndvcc = false;
 		CellTypes ct(design);
@@ -132,6 +159,29 @@ struct EdifBackend : public Backend {
 				nogndvcc = true;
 				continue;
 			}
+			if (args[argidx] == "-pidx" && argidx+1 < args.size()) {
+				always_rename = true;
+				if(args[++argidx] == "down") {
+					bounds[0]=1;bounds[1]=0;
+				}
+				else {
+					bounds[0]=0;bounds[1]=1;
+				}
+				continue;
+			}
+			if (args[argidx] == "-parray" && argidx+1 < args.size()) {
+				std::string parray;
+				always_rename = true;
+				parray = args[++argidx];
+				if (parray == "par") {
+					delim[0] = '(';delim[1] = ')';
+				} else if (parray == "ang") {
+					delim[0] = '<';delim[1] = '>';
+				} else {
+					delim[0] = '[';delim[1] = ']';
+				}
+				continue;
+			}
 			break;
 		}
 		extra_args(f, filename, args, argidx);
@@ -215,7 +265,11 @@ struct EdifBackend : public Backend {
 				if (port_it.second == 1)
 					*f << stringf("          (port %s (direction %s))\n", EDIF_DEF(port_it.first), dir);
 				else
-					*f << stringf("          (port (array %s %d) (direction %s))\n", EDIF_DEF(port_it.first), port_it.second, dir);
+				{
+					int bd[2]={0,port_it.second-1};
+					int b[2]={bd[bounds[0]],bd[bounds[1]]};
+					*f << stringf("          (port (array %s %d) (direction %s))\n", EDIF_DEFR(port_it.first, always_rename, delim, b), port_it.second, dir);
+				}
 			}
 			*f << stringf("        )\n");
 			*f << stringf("      )\n");
@@ -283,7 +337,9 @@ struct EdifBackend : public Backend {
 					RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire));
 					net_join_db[sig].insert(stringf("(portRef %s)", EDIF_REF(wire->name)));
 				} else {
-					*f << stringf("          (port (array %s %d) (direction %s))\n", EDIF_DEF(wire->name), wire->width, dir);
+					int bd[2]={0,wire->width-1};
+					int b[2]={bd[bounds[0]],bd[bounds[1]]};
+					*f << stringf("          (port (array %s %d) (direction %s))\n", EDIF_DEFR(wire->name, always_rename, delim, b), wire->width, dir);
 					for (int i = 0; i < wire->width; i++) {
 						RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire, i));
 						net_join_db[sig].insert(stringf("(portRef (member %s %d))", EDIF_REF(wire->name), i));