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analogdevices: timings for t40lp
This commit is contained in:
Lofty
parent
29140d5fd2
commit
06ca530194
1 changed files with 331 additions and 9 deletions
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@ -41,6 +41,11 @@ module INBUF(
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(I => O) = 22;
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endspecify
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`endif
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`ifdef IS_T40LP
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specify
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(I => O) = 121;
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endspecify
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`endif
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endmodule
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module OUTBUF(
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@ -57,6 +62,11 @@ module OUTBUF(
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(I => O) = 22;
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endspecify
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`endif
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`ifdef IS_T40LP
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specify
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(I => O) = 121;
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endspecify
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`endif
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endmodule
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(* abc9_lut=1 *)
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@ -68,6 +78,11 @@ module LUT1(output O, input I0);
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(I0 => O) = 22;
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endspecify
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`endif
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`ifdef IS_T40LP
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specify
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(I0 => O) = 121;
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endspecify
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`endif
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endmodule
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(* abc9_lut=2 *)
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@ -81,6 +96,12 @@ module LUT2(output O, input I0, I1);
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(I1 => O) = 22;
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endspecify
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`endif
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`ifdef IS_T40LP
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specify
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(I0 => O) = 121;
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(I1 => O) = 121;
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endspecify
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`endif
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endmodule
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(* abc9_lut=3 *)
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@ -96,6 +117,13 @@ module LUT3(output O, input I0, I1, I2);
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(I2 => O) = 22;
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endspecify
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`endif
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`ifdef IS_T40LP
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specify
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(I0 => O) = 121;
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(I1 => O) = 121;
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(I2 => O) = 121;
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endspecify
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`endif
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endmodule
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(* abc9_lut=4 *)
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@ -113,6 +141,14 @@ module LUT4(output O, input I0, I1, I2, I3);
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(I3 => O) = 22;
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endspecify
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`endif
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`ifdef IS_T40LP
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specify
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(I0 => O) = 121;
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(I1 => O) = 121;
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(I2 => O) = 121;
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(I3 => O) = 121;
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endspecify
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`endif
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endmodule
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(* abc9_lut=5 *)
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@ -132,6 +168,15 @@ module LUT5(output O, input I0, I1, I2, I3, I4);
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(I4 => O) = 22;
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endspecify
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`endif
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`ifdef IS_T40LP
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specify
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(I0 => O) = 121;
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(I1 => O) = 121;
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(I2 => O) = 121;
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(I3 => O) = 121;
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(I4 => O) = 121;
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endspecify
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`endif
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endmodule
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(* abc9_lut=6 *)
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@ -153,6 +198,16 @@ module LUT6(output O, input I0, I1, I2, I3, I4, I5);
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(I5 => O) = 22;
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endspecify
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`endif
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`ifdef IS_T40LP
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specify
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(I0 => O) = 121;
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(I1 => O) = 121;
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(I2 => O) = 121;
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(I3 => O) = 121;
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(I4 => O) = 121;
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(I5 => O) = 121;
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endspecify
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`endif
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endmodule
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module LUT6_D(output O6, output O5, input I0, I1, I2, I3, I4, I5);
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@ -187,6 +242,17 @@ module \$__ABC9_LUT7 (output O, input I0, I1, I2, I3, I4, I5, I6);
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(I6 => O) = 0 + 51 /* LUTMUX7.S */;
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endspecify
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`endif
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`ifdef IS_T40LP
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specify
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(I0 => O) = 121 + 140 /* LUTMUX7.I0 */;
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(I1 => O) = 121 + 140 /* LUTMUX7.I0 */;
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(I2 => O) = 121 + 140 /* LUTMUX7.I0 */;
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(I3 => O) = 121 + 140 /* LUTMUX7.I0 */;
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(I4 => O) = 121 + 140 /* LUTMUX7.I0 */;
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(I5 => O) = 121 + 140 /* LUTMUX7.I0 */;
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(I6 => O) = 0 + 162 /* LUTMUX7.S */;
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endspecify
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`endif
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`endif
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endmodule
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@ -207,6 +273,18 @@ module \$__ABC9_LUT8 (output O, input I0, I1, I2, I3, I4, I5, I6, I7);
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(I7 => O) = 0 + 0 + 58 /* LUTMUX8.S */;
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endspecify
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`endif
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`ifdef IS_T40LP
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specify
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(I0 => O) = 121 + 140 /* LUTMUX7.I0 */ + 146 /* LUTMUX8.I1 */;
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(I1 => O) = 121 + 140 /* LUTMUX7.I0 */ + 146 /* LUTMUX8.I1 */;
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(I2 => O) = 121 + 140 /* LUTMUX7.I0 */ + 146 /* LUTMUX8.I1 */;
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(I3 => O) = 121 + 140 /* LUTMUX7.I0 */ + 146 /* LUTMUX8.I1 */;
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(I4 => O) = 121 + 140 /* LUTMUX7.I0 */ + 146 /* LUTMUX8.I1 */;
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(I5 => O) = 121 + 140 /* LUTMUX7.I0 */ + 146 /* LUTMUX8.I1 */;
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(I6 => O) = 0 + 162 /* LUTMUX7.S */ + 146 /* LUTMUX8.I1 */;
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(I7 => O) = 0 + 0 + 181 /* LUTMUX8.S */;
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endspecify
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`endif
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`endif
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endmodule
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@ -220,6 +298,13 @@ module LUTMUX7(output O, input I0, I1, S);
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(S => O) = 51;
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endspecify
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`endif
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`ifdef IS_T40LP
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specify
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(I0 => O) = 140;
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(I1 => O) = 140;
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(S => O) = 162;
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endspecify
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`endif
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endmodule
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(* abc9_box, lib_whitebox *)
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@ -232,6 +317,13 @@ module LUTMUX8(output O, input I0, I1, S);
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(S => O) = 58;
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endspecify
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`endif
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`ifdef IS_T40LP
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specify
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(I0 => O) = 140;
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(I1 => O) = 146;
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(S => O) = 181;
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endspecify
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`endif
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endmodule
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(* abc9_box, lib_whitebox *)
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@ -297,6 +389,54 @@ module CRY4(
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(CI => CO[3]) = 20;
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endspecify
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`endif
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`ifdef IS_T40LP
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specify
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(S[0] => O[0]) = 128;
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(CI => O[0]) = 122;
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(DI[0] => O[1]) = 268;
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(S[0] => O[1]) = 256;
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(S[1] => O[1]) = 141;
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(CI => O[1]) = 173;
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(DI[0] => O[2]) = 344;
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(DI[1] => O[2]) = 320;
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(S[0] => O[2]) = 271;
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(S[1] => O[2]) = 225;
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(S[2] => O[2]) = 129;
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(CI => O[2]) = 223;
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(DI[0] => O[3]) = 371;
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(DI[1] => O[3]) = 383;
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(DI[2] => O[3]) = 327;
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(S[0] => O[3]) = 342;
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(S[1] => O[3]) = 327;
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(S[2] => O[3]) = 273;
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(S[3] => O[3]) = 145;
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(CI => O[3]) = 301;
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(DI[0] => CO[0]) = 243;
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(S[0] => CO[0]) = 136;
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(CI => CO[0]) = 119;
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(DI[0] => CO[1]) = 242;
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(DI[1] => CO[1]) = 251;
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(S[0] => CO[1]) = 220;
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(S[1] => CO[1]) = 159;
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(CI => CO[1]) = 155;
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(DI[0] => CO[2]) = 275;
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(DI[1] => CO[2]) = 241;
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(DI[2] => CO[2]) = 231;
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(S[0] => CO[2]) = 238;
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(S[1] => CO[2]) = 197;
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(S[2] => CO[2]) = 167;
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(CI => CO[2]) = 197;
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(DI[0] => CO[3]) = 294;
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(DI[1] => CO[3]) = 303;
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(DI[2] => CO[3]) = 317;
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(DI[3] => CO[3]) = 205;
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(S[0] => CO[3]) = 250;
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(S[1] => CO[3]) = 292;
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(S[2] => CO[3]) = 231;
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(S[3] => CO[3]) = 178;
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(CI => CO[3]) = 229;
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endspecify
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`endif
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endmodule
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(* abc9_box, lib_whitebox *)
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@ -306,13 +446,17 @@ module CRY4INIT(
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(* abc9_carry *)
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input CYINIT
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);
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assign CO = CYINIT;
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`ifdef IS_T16FFC
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specify
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(CYINIT => CO) = 72;
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endspecify
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`endif
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assign CO = CYINIT;
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`ifdef IS_T40LP
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specify
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(CYINIT => CO) = 205;
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endspecify
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`endif
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endmodule
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// Flip-flops.
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@ -338,6 +482,17 @@ module FFRE (
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if (!R && CE) (posedge C => (Q : D)) = 280;
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endspecify
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`endif
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`ifdef IS_T40LP
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specify
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$setup(D , posedge C, 119);
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$setup(CE, posedge C, 385);
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$setup(R , posedge C, 565);
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// HACK: no clock-to-Q timings; using FFCE timing
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if (R) (posedge C => (Q : 1'b0)) = 689;
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// HACK: no clock-to-Q timings; using FFCE timing
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if (!R && CE) (posedge C => (Q : D)) = 689;
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endspecify
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`endif
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endmodule
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(* abc9_flop, lib_whitebox *)
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@ -361,6 +516,17 @@ module FFRE_N (
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if (!R && CE) (negedge C => (Q : D)) = 280;
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endspecify
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`endif
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`ifdef IS_T40LP
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specify
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$setup(D , negedge C, 119);
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$setup(CE, negedge C, 385);
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$setup(R , negedge C, 565);
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// HACK: no clock-to-Q timings; using FFCE timing
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if (R) (negedge C => (Q : 1'b0)) = 689;
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// HACK: no clock-to-Q timings; using FFCE timing
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if (!R && CE) (negedge C => (Q : D)) = 689;
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endspecify
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`endif
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endmodule
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module FFSE (
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@ -383,6 +549,17 @@ module FFSE (
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if (!S && CE) (posedge C => (Q : D)) = 280;
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endspecify
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`endif
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`ifdef IS_T40LP
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specify
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$setup(D , posedge C, 119);
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$setup(CE, posedge C, 385);
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$setup(S , posedge C, 584);
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// HACK: no clock-to-Q timings; using FFCE timing
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if (S) (negedge C => (Q : 1'b1)) = 689;
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// HACK: no clock-to-Q timings; using FFCE timing
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if (!S && CE) (posedge C => (Q : D)) = 689;
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endspecify
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`endif
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endmodule
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module FFSE_N (
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@ -405,6 +582,17 @@ module FFSE_N (
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if (!S && CE) (negedge C => (Q : D)) = 280;
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endspecify
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`endif
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`ifdef IS_T40LP
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specify
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$setup(D , negedge C, 119);
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$setup(CE, negedge C, 385);
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$setup(S , negedge C, 584);
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// HACK: no clock-to-Q timings; using FFCE timing
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if (S) (negedge C => (Q : 1'b1)) = 689;
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// HACK: no clock-to-Q timings; using FFCE timing
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if (!S && CE) (negedge C => (Q : D)) = 689;
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endspecify
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`endif
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endmodule
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module FFCE (
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@ -421,10 +609,17 @@ module FFCE (
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`ifdef IS_T16FFC
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specify
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$setup(D , posedge C, 31);
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$setup(CE , posedge C, 122);
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$setup(CE, posedge C, 122);
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if (!CLR && CE) (posedge C => (Q : D)) = 280;
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endspecify
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`endif
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`ifdef IS_T40LP
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specify
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$setup(D , posedge C, 119);
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$setup(CE, posedge C, 385);
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if (!CLR && CE) (posedge C => (Q : D)) = 689;
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endspecify
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`endif
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endmodule
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module FFCE_N (
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@ -441,10 +636,17 @@ module FFCE_N (
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`ifdef IS_T16FFC
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specify
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$setup(D , negedge C, 31);
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$setup(CE , negedge C, 122);
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$setup(CE, negedge C, 122);
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if (!CLR && CE) (negedge C => (Q : D)) = 280;
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endspecify
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`endif
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`ifdef IS_T40LP
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specify
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$setup(D , negedge C, 119);
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$setup(CE, negedge C, 385);
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if (!CLR && CE) (negedge C => (Q : D)) = 689;
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endspecify
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`endif
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endmodule
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module FFPE (
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@ -461,10 +663,18 @@ module FFPE (
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`ifdef IS_T16FFC
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specify
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$setup(D , posedge C, 31);
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$setup(CE , posedge C, 122);
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$setup(CE, posedge C, 122);
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if (!PRE && CE) (posedge C => (Q : D)) = 291;
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endspecify
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`endif
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`ifdef IS_T40LP
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specify
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$setup(D , posedge C, 119);
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$setup(CE, posedge C, 385);
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// HACK: no clock-to-Q timings; using FFPE_N timing
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if (!PRE && CE) (posedge C => (Q : D)) = 712;
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endspecify
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`endif
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endmodule
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module FFPE_N (
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@ -485,6 +695,15 @@ module FFPE_N (
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if (!PRE && CE) (negedge C => (Q : D)) = 291;
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endspecify
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`endif
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`ifdef IS_T40LP
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specify
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// HACK: no D setup time; using FFPE timing
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$setup(D , negedge C, 119);
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// HACK: no CE setup time; using FFPE timing
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$setup(CE, negedge C, 385);
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if (!PRE && CE) (negedge C => (Q : D)) = 712;
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endspecify
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`endif
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endmodule
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// LUTRAM.
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@ -507,6 +726,7 @@ module RAMS32X1 (
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always @(posedge WCLK) if (WE) mem[a] <= D;
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`ifdef IS_T16FFC
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specify
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// HACK: no setup timing
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$setup(A0, posedge WCLK, 0);
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$setup(A1, posedge WCLK, 0);
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$setup(A2, posedge WCLK, 0);
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@ -522,6 +742,24 @@ module RAMS32X1 (
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(posedge WCLK => (O : D)) = 813;
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endspecify
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`endif
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`ifdef IS_T40LP
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specify
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// HACK: no setup timing
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$setup(A0, posedge WCLK, 0);
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$setup(A1, posedge WCLK, 0);
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$setup(A2, posedge WCLK, 0);
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$setup(A3, posedge WCLK, 0);
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$setup(A4, posedge WCLK, 0);
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$setup(D, posedge WCLK, 0);
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$setup(WE, posedge WCLK, 0);
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(A0 => O) = 168;
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(A1 => O) = 168;
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(A2 => O) = 168;
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(A3 => O) = 168;
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(A4 => O) = 168;
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(posedge WCLK => (O : D)) = 1586;
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endspecify
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`endif
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endmodule
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(* abc9_box, lib_whitebox *)
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@ -540,6 +778,7 @@ module RAMS64X1 (
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always @(posedge WCLK) if (WE) mem[a] <= D;
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`ifdef IS_T16FFC
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specify
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// HACK: no setup timing
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$setup(A0, posedge WCLK, 0);
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$setup(A1, posedge WCLK, 0);
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$setup(A2, posedge WCLK, 0);
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@ -557,6 +796,26 @@ module RAMS64X1 (
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(posedge WCLK => (O : D)) = 762;
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endspecify
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`endif
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`ifdef IS_T40LP
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specify
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// HACK: no setup timing
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$setup(A0, posedge WCLK, 0);
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$setup(A1, posedge WCLK, 0);
|
||||
$setup(A2, posedge WCLK, 0);
|
||||
$setup(A3, posedge WCLK, 0);
|
||||
$setup(A4, posedge WCLK, 0);
|
||||
$setup(A5, posedge WCLK, 0);
|
||||
$setup(D, posedge WCLK, 0);
|
||||
$setup(WE, posedge WCLK, 0);
|
||||
(A0 => O) = 466;
|
||||
(A1 => O) = 466;
|
||||
(A2 => O) = 466;
|
||||
(A3 => O) = 466;
|
||||
(A4 => O) = 466;
|
||||
(A5 => O) = 187;
|
||||
(posedge WCLK => (O : D)) = 1730;
|
||||
endspecify
|
||||
`endif
|
||||
endmodule
|
||||
|
||||
// Dual port.
|
||||
|
|
@ -580,12 +839,12 @@ module RAMD32X1 (
|
|||
always @(posedge WCLK) if (WE) mem[a] <= D;
|
||||
`ifdef IS_T16FFC
|
||||
specify
|
||||
// HACK: no setup timing
|
||||
$setup(A0, posedge WCLK, 0);
|
||||
$setup(A1, posedge WCLK, 0);
|
||||
$setup(A2, posedge WCLK, 0);
|
||||
$setup(A3, posedge WCLK, 0);
|
||||
$setup(A4, posedge WCLK, 0);
|
||||
// HACK: No timing arcs for DPRAn; using ones for An
|
||||
$setup(DPRA0, posedge WCLK, 0);
|
||||
$setup(DPRA1, posedge WCLK, 0);
|
||||
$setup(DPRA2, posedge WCLK, 0);
|
||||
|
|
@ -594,6 +853,7 @@ module RAMD32X1 (
|
|||
$setup(D, posedge WCLK, 0);
|
||||
$setup(WE, posedge WCLK, 0);
|
||||
// HACK: No timing arcs for SPO; using ones for DPO
|
||||
// (are we meant to use the single-port timings here?)
|
||||
(A0 => SPO) = 66;
|
||||
(A1 => SPO) = 66;
|
||||
(A2 => SPO) = 66;
|
||||
|
|
@ -608,6 +868,37 @@ module RAMD32X1 (
|
|||
(posedge WCLK => (DPO : D)) = 813;
|
||||
endspecify
|
||||
`endif
|
||||
`ifdef IS_T40LP
|
||||
specify
|
||||
// HACK: no setup timing
|
||||
$setup(A0, posedge WCLK, 0);
|
||||
$setup(A1, posedge WCLK, 0);
|
||||
$setup(A2, posedge WCLK, 0);
|
||||
$setup(A3, posedge WCLK, 0);
|
||||
$setup(A4, posedge WCLK, 0);
|
||||
$setup(DPRA0, posedge WCLK, 0);
|
||||
$setup(DPRA1, posedge WCLK, 0);
|
||||
$setup(DPRA2, posedge WCLK, 0);
|
||||
$setup(DPRA3, posedge WCLK, 0);
|
||||
$setup(DPRA4, posedge WCLK, 0);
|
||||
$setup(D, posedge WCLK, 0);
|
||||
$setup(WE, posedge WCLK, 0);
|
||||
// HACK: No timing arcs for SPO; using ones for DPO
|
||||
// (are we meant to use the single-port timings here?)
|
||||
(A0 => SPO) = 142;
|
||||
(A1 => SPO) = 142;
|
||||
(A2 => SPO) = 142;
|
||||
(A3 => SPO) = 142;
|
||||
(A4 => SPO) = 142;
|
||||
(DPRA0 => DPO) = 142;
|
||||
(DPRA1 => DPO) = 142;
|
||||
(DPRA2 => DPO) = 142;
|
||||
(DPRA3 => DPO) = 142;
|
||||
(DPRA4 => DPO) = 142;
|
||||
(posedge WCLK => (SPO : D)) = 1586;
|
||||
(posedge WCLK => (DPO : D)) = 1586;
|
||||
endspecify
|
||||
`endif
|
||||
endmodule
|
||||
|
||||
(* abc9_box, lib_whitebox *)
|
||||
|
|
@ -629,13 +920,13 @@ module RAMD64X1 (
|
|||
always @(posedge WCLK) if (WE) mem[a] <= D;
|
||||
`ifdef IS_T16FFC
|
||||
specify
|
||||
// HACK: no setup timing
|
||||
$setup(A0, posedge WCLK, 0);
|
||||
$setup(A1, posedge WCLK, 0);
|
||||
$setup(A2, posedge WCLK, 0);
|
||||
$setup(A3, posedge WCLK, 0);
|
||||
$setup(A4, posedge WCLK, 0);
|
||||
$setup(A5, posedge WCLK, 0);
|
||||
// HACK: No timing arcs for DPRAn; using ones for An
|
||||
$setup(DPRA0, posedge WCLK, 0);
|
||||
$setup(DPRA1, posedge WCLK, 0);
|
||||
$setup(DPRA2, posedge WCLK, 0);
|
||||
|
|
@ -660,6 +951,39 @@ module RAMD64X1 (
|
|||
(posedge WCLK => (DPO : D)) = 737;
|
||||
endspecify
|
||||
`endif
|
||||
`ifdef IS_T40LP
|
||||
specify
|
||||
// HACK: no setup timing
|
||||
$setup(A0, posedge WCLK, 0);
|
||||
$setup(A1, posedge WCLK, 0);
|
||||
$setup(A2, posedge WCLK, 0);
|
||||
$setup(A3, posedge WCLK, 0);
|
||||
$setup(A4, posedge WCLK, 0);
|
||||
$setup(A5, posedge WCLK, 0);
|
||||
$setup(DPRA0, posedge WCLK, 0);
|
||||
$setup(DPRA1, posedge WCLK, 0);
|
||||
$setup(DPRA2, posedge WCLK, 0);
|
||||
$setup(DPRA3, posedge WCLK, 0);
|
||||
$setup(DPRA4, posedge WCLK, 0);
|
||||
$setup(DPRA5, posedge WCLK, 0);
|
||||
$setup(D, posedge WCLK, 0);
|
||||
$setup(WE, posedge WCLK, 0);
|
||||
(A0 => SPO) = 466;
|
||||
(A1 => SPO) = 466;
|
||||
(A2 => SPO) = 466;
|
||||
(A3 => SPO) = 466;
|
||||
(A4 => SPO) = 466;
|
||||
(A5 => SPO) = 187;
|
||||
(DPRA0 => DPO) = 380;
|
||||
(DPRA1 => DPO) = 380;
|
||||
(DPRA2 => DPO) = 380;
|
||||
(DPRA3 => DPO) = 380;
|
||||
(DPRA4 => DPO) = 380;
|
||||
(DPRA5 => DPO) = 195;
|
||||
(posedge WCLK => (SPO : D)) = 1730;
|
||||
(posedge WCLK => (DPO : D)) = 1799;
|
||||
endspecify
|
||||
`endif
|
||||
endmodule
|
||||
|
||||
// Shift registers.
|
||||
|
|
@ -677,7 +1001,6 @@ module SRG16E (
|
|||
reg [15:0] r = INIT;
|
||||
assign Q = r[{A3,A2,A1,A0}];
|
||||
always @(posedge CLK) if (CE) r <= { r[14:0], D };
|
||||
`ifdef IS_T16FFC
|
||||
specify
|
||||
$setup(D , posedge CLK, 173);
|
||||
if (CE) (posedge CLK => (Q : D)) = 1472;
|
||||
|
|
@ -687,7 +1010,6 @@ module SRG16E (
|
|||
(A2 => Q) = 407;
|
||||
(A3 => Q) = 238;
|
||||
endspecify
|
||||
`endif
|
||||
endmodule
|
||||
|
||||
// DSP
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue